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Commit c7980010 authored by Jordan Crouse's avatar Jordan Crouse Committed by Andy Gross
Browse files

arm64: dts: sdm845: Add gpu and gmu device nodes 



Add the nodes to describe the Adreno GPU and GMU devices for sdm845.

Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
Tested-by: default avatarDouglas Anderson <dianders@chromium.org>
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
[bjorn: Added required gx power-domain]
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>

Signed-off-by: default avatarAndy Gross <agross@kernel.org>
parent 9000a55b

arch/arm64/boot/dts/qcom/sdm845.dtsi

+123 −0
Original line number Diff line number Diff line
@@ -2104,6 +2104,129 @@ 
			};

		};



		gpu@5000000 {

			compatible = "qcom,adreno-630.2", "qcom,adreno";

			#stream-id-cells = <16>;



			reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;

			reg-names = "kgsl_3d0_reg_memory", "cx_mem";



			/*

			 * Look ma, no clocks! The GPU clocks and power are

			 * controlled entirely by the GMU

			 */



			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;



			iommus = <&adreno_smmu 0>;



			operating-points-v2 = <&gpu_opp_table>;



			qcom,gmu = <&gmu>;



			gpu_opp_table: opp-table {

				compatible = "operating-points-v2";



				opp-710000000 {

					opp-hz = /bits/ 64 <710000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;

				};



				opp-675000000 {

					opp-hz = /bits/ 64 <675000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;

				};



				opp-596000000 {

					opp-hz = /bits/ 64 <596000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;

				};



				opp-520000000 {

					opp-hz = /bits/ 64 <520000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;

				};



				opp-414000000 {

					opp-hz = /bits/ 64 <414000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

				};



				opp-342000000 {

					opp-hz = /bits/ 64 <342000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;

				};



				opp-257000000 {

					opp-hz = /bits/ 64 <257000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;

				};

			};

		};



		adreno_smmu: iommu@5040000 {

			compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";

			reg = <0 0x5040000 0 0x10000>;

			#iommu-cells = <1>;

			#global-interrupts = <2>;

			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;

			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,

			         <&gcc GCC_GPU_CFG_AHB_CLK>;

			clock-names = "bus", "iface";



			power-domains = <&gpucc GPU_CX_GDSC>;

		};



		gmu: gmu@506a000 {

			compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";



			reg = <0 0x506a000 0 0x30000>,

			      <0 0xb280000 0 0x10000>,

			      <0 0xb480000 0 0x10000>;

			reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";



			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hfi", "gmu";



			clocks = <&gpucc GPU_CC_CX_GMU_CLK>,

			         <&gpucc GPU_CC_CXO_CLK>,

				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,

				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;

			clock-names = "gmu", "cxo", "axi", "memnoc";



			power-domains = <&gpucc GPU_CX_GDSC>,

					<&gpucc GPU_GX_GDSC>;

			power-domain-names = "cx", "gx";



			iommus = <&adreno_smmu 5>;



			operating-points-v2 = <&gmu_opp_table>;



			gmu_opp_table: opp-table {

				compatible = "operating-points-v2";



				opp-400000000 {

					opp-hz = /bits/ 64 <400000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;

				};



				opp-200000000 {

					opp-hz = /bits/ 64 <200000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;

				};

			};

		};



		dispcc: clock-controller@af00000 {

			compatible = "qcom,sdm845-dispcc";

			reg = <0 0x0af00000 0 0x10000>;