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Commit c78275f3 authored by Richard Cochran's avatar Richard Cochran Committed by John Stultz
Browse files

ptp: Added a clock that uses the eTSEC found on the MPC85xx. 



The eTSEC includes a PTP clock with quite a few features. This patch adds
support for the basic clock adjustment functions, plus two external time
stamps, one alarm, and the PPS callback.

Signed-off-by: default avatarRichard Cochran <richard.cochran@omicron.at>
Acked-by: default avatarDavid S. Miller <davem@davemloft.net>
Acked-by: default avatarJohn Stultz <john.stultz@linaro.org>
Signed-off-by: default avatarJohn Stultz <john.stultz@linaro.org>
parent d94ba80e

Documentation/devicetree/bindings/net/fsl-tsec-phy.txt

+54 −0
Original line number Diff line number Diff line
@@ -74,3 +74,57 @@ Example: 
		interrupt-parent = <&mpic>;

		phy-handle = <&phy0>

	};



* Gianfar PTP clock nodes



General Properties:



  - compatible   Should be "fsl,etsec-ptp"

  - reg          Offset and length of the register set for the device

  - interrupts   There should be at least two interrupts. Some devices

                 have as many as four PTP related interrupts.



Clock Properties:



  - fsl,tclk-period  Timer reference clock period in nanoseconds.

  - fsl,tmr-prsc     Prescaler, divides the output clock.

  - fsl,tmr-add      Frequency compensation value.

  - fsl,tmr-fiper1   Fixed interval period pulse generator.

  - fsl,tmr-fiper2   Fixed interval period pulse generator.

  - fsl,max-adj      Maximum frequency adjustment in parts per billion.



  These properties set the operational parameters for the PTP

  clock. You must choose these carefully for the clock to work right.

  Here is how to figure good values:



  TimerOsc     = system clock               MHz

  tclk_period  = desired clock period       nanoseconds

  NominalFreq  = 1000 / tclk_period         MHz

  FreqDivRatio = TimerOsc / NominalFreq     (must be greater that 1.0)

  tmr_add      = ceil(2^32 / FreqDivRatio)

  OutputClock  = NominalFreq / tmr_prsc     MHz

  PulseWidth   = 1 / OutputClock            microseconds

  FiperFreq1   = desired frequency in Hz

  FiperDiv1    = 1000000 * OutputClock / FiperFreq1

  tmr_fiper1   = tmr_prsc * tclk_period * FiperDiv1 - tclk_period

  max_adj      = 1000000000 * (FreqDivRatio - 1.0) - 1



  The calculation for tmr_fiper2 is the same as for tmr_fiper1. The

  driver expects that tmr_fiper1 will be correctly set to produce a 1

  Pulse Per Second (PPS) signal, since this will be offered to the PPS

  subsystem to synchronize the Linux clock.



Example:



	ptp_clock@24E00 {

		compatible = "fsl,etsec-ptp";

		reg = <0x24E00 0xB0>;

		interrupts = <12 0x8 13 0x8>;

		interrupt-parent = < &ipic >;

		fsl,tclk-period = <10>;

		fsl,tmr-prsc    = <100>;

		fsl,tmr-add     = <0x999999A4>;

		fsl,tmr-fiper1  = <0x3B9AC9F6>;

		fsl,tmr-fiper2  = <0x00018696>;

		fsl,max-adj     = <659999998>;

	};

arch/powerpc/boot/dts/mpc8313erdb.dts

+13 −0
Original line number Diff line number Diff line
@@ -176,6 +176,19 @@ 
			sleep = <&pmc 0x00300000>;

		};



		ptp_clock@24E00 {

			compatible = "fsl,etsec-ptp";

			reg = <0x24E00 0xB0>;

			interrupts = <12 0x8 13 0x8>;

			interrupt-parent = < &ipic >;

			fsl,tclk-period = <10>;

			fsl,tmr-prsc    = <100>;

			fsl,tmr-add     = <0x999999A4>;

			fsl,tmr-fiper1  = <0x3B9AC9F6>;

			fsl,tmr-fiper2  = <0x00018696>;

			fsl,max-adj     = <659999998>;

		};



		enet0: ethernet@24000 {

			#address-cells = <1>;

			#size-cells = <1>;

arch/powerpc/boot/dts/mpc8572ds.dts

+13 −0
Original line number Diff line number Diff line
@@ -324,6 +324,19 @@ 
			};

		};



		ptp_clock@24E00 {

			compatible = "fsl,etsec-ptp";

			reg = <0x24E00 0xB0>;

			interrupts = <68 2 69 2 70 2 71 2>;

			interrupt-parent = < &mpic >;

			fsl,tclk-period = <5>;

			fsl,tmr-prsc = <200>;

			fsl,tmr-add = <0xAAAAAAAB>;

			fsl,tmr-fiper1 = <0x3B9AC9FB>;

			fsl,tmr-fiper2 = <0x3B9AC9FB>;

			fsl,max-adj = <499999999>;

		};



		enet0: ethernet@24000 {

			#address-cells = <1>;

			#size-cells = <1>;

arch/powerpc/boot/dts/p2020ds.dts

+13 −0
Original line number Diff line number Diff line
@@ -178,6 +178,19 @@ 


		};



		ptp_clock@24E00 {

			compatible = "fsl,etsec-ptp";

			reg = <0x24E00 0xB0>;

			interrupts = <68 2 69 2 70 2>;

			interrupt-parent = < &mpic >;

			fsl,tclk-period = <5>;

			fsl,tmr-prsc = <200>;

			fsl,tmr-add = <0xCCCCCCCD>;

			fsl,tmr-fiper1 = <0x3B9AC9FB>;

			fsl,tmr-fiper2 = <0x0001869B>;

			fsl,max-adj = <249999999>;

		};



		enet0: ethernet@24000 {

			tbi-handle = <&tbi0>;

			phy-handle = <&phy0>;

arch/powerpc/boot/dts/p2020rdb.dts

+13 −0
Original line number Diff line number Diff line
@@ -224,6 +224,19 @@ 
			status = "disabled";

		};



		ptp_clock@24E00 {

			compatible = "fsl,etsec-ptp";

			reg = <0x24E00 0xB0>;

			interrupts = <68 2 69 2 70 2>;

			interrupt-parent = < &mpic >;

			fsl,tclk-period = <5>;

			fsl,tmr-prsc = <200>;

			fsl,tmr-add = <0xCCCCCCCD>;

			fsl,tmr-fiper1 = <0x3B9AC9FB>;

			fsl,tmr-fiper2 = <0x0001869B>;

			fsl,max-adj = <249999999>;

		};



		enet0: ethernet@24000 {

			fixed-link = <1 1 1000 0 0>;

			phy-connection-type = "rgmii-id";