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Commit c77e17b5 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Do not modify UCHE_CMDQ_CONFIG register for A660"

parents bcf1293b a0badd2c
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+0 −1
Original line number Diff line number Diff line
@@ -726,7 +726,6 @@
#define A6XX_UCHE_PERFCTR_UCHE_SEL_10       0xE26
#define A6XX_UCHE_PERFCTR_UCHE_SEL_11       0xE27
#define A6XX_UCHE_GBIF_GX_CONFIG            0xE3A
#define A6XX_UCHE_CMDQ_CONFIG               0xE3C

/* SP registers */
#define A6XX_SP_ADDR_MODE_CNTL              0xAE01
+6 −12
Original line number Diff line number Diff line
@@ -102,16 +102,14 @@ static u32 a6xx_ifpc_pwrup_reglist[] = {
	A6XX_CP_AHB_CNTL,
};

/* a620 and a650 need to program A6XX_CP_PROTECT_REG_47 for the infinite span */
/*
 * a620, a650 and a660 need to program A6XX_CP_PROTECT_REG_47
 * for the infinite span
 */
static u32 a650_pwrup_reglist[] = {
	A6XX_CP_PROTECT_REG + 47,
};

static u32 a660_pwrup_reglist[] = {
	A6XX_CP_PROTECT_REG + 47,
	A6XX_UCHE_CMDQ_CONFIG,
};

static u32 a615_pwrup_reglist[] = {
	A6XX_UCHE_GBIF_GX_CONFIG,
};
@@ -319,10 +317,8 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev)
		reglist[items++] = REGLIST(a612_pwrup_reglist);
	else if (adreno_is_a615_family(adreno_dev))
		reglist[items++] = REGLIST(a615_pwrup_reglist);
	else if (adreno_is_a650(adreno_dev) || adreno_is_a620(adreno_dev))
	else if (adreno_is_a650_family(adreno_dev))
		reglist[items++] = REGLIST(a650_pwrup_reglist);
	else if (adreno_is_a660(adreno_dev))
		reglist[items++] = REGLIST(a660_pwrup_reglist);

	/*
	 * For each entry in each of the lists, write the offset and the current
@@ -621,10 +617,8 @@ static void a6xx_start(struct adreno_device *adreno_dev)

	a6xx_llc_enable_overrides(adreno_dev);

	if (adreno_is_a660(adreno_dev)) {
	if (adreno_is_a660(adreno_dev))
		kgsl_regwrite(device, A6XX_CP_CHICKEN_DBG, 0x1);
		kgsl_regwrite(device, A6XX_UCHE_CMDQ_CONFIG, 0x6632f);
	}

	if (adreno_is_a660v1(adreno_dev))
		kgsl_regwrite(device, A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);