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Commit c738be0d authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add eMMC platform support for Monaco variants"

parents 63469e92 7a42f649

qcom/monaco-idp-v1.dtsi

+18 −0
Original line number Diff line number Diff line 


&sdhc_1 {

	status = "ok";



	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&sdc1_on>;

	pinctrl-1 = <&sdc1_off>;



	vdd-supply = <&L25A>;

	qcom,vdd-voltage-level = <2950000 2950000>;

	qcom,vdd-current-level = <0 270000>;



	vdd-io-supply = <&L15A>;

	qcom,vdd-io-always-on;

	qcom,vdd-io-lpm-sup;

	qcom,vdd-io-voltage-level = <1800000 1800000>;

	qcom,vdd-io-current-level = <0 250000>;

};

qcom/monaco-pinctrl.dtsi

+42 −42
Original line number Diff line number Diff line
@@ -777,7 +777,7 @@ 
				};

			};

		};

	};



		/* SDC pin type */

		sdc1_on: sdc1_on {

			clk {
@@ -828,5 +828,5 @@ 
				bias-pull-down;

			};

		};



	};

};

qcom/monaco-rumi.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -48,6 +48,10 @@ 
	cap-mmc-highspeed;

	max-frequency = <50000000>;



	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&sdc1_on>;

	pinctrl-1 = <&sdc1_off>;



	vdd-supply = <&L25A>;

	qcom,vdd-voltage-level = <2950000 2950000>;

	qcom,vdd-current-level = <0 270000>;

qcom/monaco-standalone-idp-v1.dtsi

+18 −0
Original line number Diff line number Diff line 


&sdhc_1 {

	status = "ok";



	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&sdc1_on>;

	pinctrl-1 = <&sdc1_off>;



	vdd-supply = <&L25A>;

	qcom,vdd-voltage-level = <2950000 2950000>;

	qcom,vdd-current-level = <0 270000>;



	vdd-io-supply = <&L15A>;

	qcom,vdd-io-always-on;

	qcom,vdd-io-lpm-sup;

	qcom,vdd-io-voltage-level = <1800000 1800000>;

	qcom,vdd-io-current-level = <0 250000>;

};

qcom/monaco.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -1234,6 +1234,14 @@ 
		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */

		qcom,dll-hsr-list = <0x000F642E 0x0 0x01 0x2c010800 0x80040868>;



		qcom,devfreq,freq-table = <50000000 200000000>;

		qcom,scaling-lower-bus-speed-mode = "DDR52";



		mmc-ddr-1_8v;

		mmc-hs200-1_8v;

		mmc-hs400-1_8v;

		mmc-hs400-enhanced-strobe;



		no-sd;

		no-sdio;
@@ -1241,6 +1249,12 @@ 
		non-removable;

		supports-cqe;



		cap-mmc-hw-reset;



		/* Add dt entry for gcc hw reset */

		resets = <&gcc GCC_SDCC1_BCR>;

		reset-names = "core_reset";



		status = "disabled";



		qos0 {