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Commit c7229b60 authored by Thor Thayer's avatar Thor Thayer Committed by Borislav Petkov
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Documentation: dt: socfpga: Add Stratix10 ECC Manager binding



Add the device tree bindings needed to support the Stratix10 ECC Manager
and SDRAM ECC.

Signed-off-by: default avatarThor Thayer <thor.thayer@linux.intel.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: catalin.marinas@arm.com
Cc: devicetree@vger.kernel.org
Cc: dinguyen@kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: mchehab@kernel.org
Cc: will.deacon@arm.com
Link: http://lkml.kernel.org/r/1524854238-19394-2-git-send-email-thor.thayer@linux.intel.com


Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
parent 1e9e31cf
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+35 −0
Original line number Diff line number Diff line
@@ -231,3 +231,38 @@ Example:
				     <48 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

Stratix10 SoCFPGA ECC Manager
The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
in a shared register similar to the Arria10. However, ECC requires
access to registers that can only be read from Secure Monitor with
SMC calls. Therefore the device tree is slightly different.

Required Properties:
- compatible : Should be "altr,socfpga-s10-ecc-manager"
- interrupts : Should be single bit error interrupt, then double bit error
	interrupt.
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
- #interrupt-cells : must be set to 2.

Subcomponents:

SDRAM ECC
Required Properties:
- compatible : Should be "altr,sdram-edac-s10"
- interrupts : Should be single bit error interrupt, then double bit error
	interrupt, in this order.

Example:

	eccmgr {
		compatible = "altr,socfpga-s10-ecc-manager";
		interrupts = <0 15 4>, <0 95 4>;
		interrupt-controller;
		#interrupt-cells = <2>;

		sdramedac {
			compatible = "altr,sdram-edac-s10";
			interrupts = <16 4>, <48 4>;
		};
	};