Loading drivers/clk/qcom/Kconfig +9 −0 Original line number Diff line number Diff line Loading @@ -793,6 +793,15 @@ config SA_DEBUGCC_DIREWOLF Say Y if you want to support the debug clocks such as clock measurement functionality. config SDW_DISPCC_MONACO tristate "MONACO Display Clock Controller" depends on SDW_GCC_MONACO help Support for the display clock controller on Qualcomm Technologies, Inc. MONACO devices. Say Y if you want to support display devices and functionality such as splash screen. endif config VIRTIO_CLK Loading drivers/clk/qcom/Makefile +3 −2 Original line number Diff line number Diff line Loading @@ -69,12 +69,13 @@ obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o obj-$(CONFIG_SDW_DISPCC_MONACO) += dispcc-monaco.o obj-$(CONFIG_SDW_GCC_MONACO) += gcc-monaco.o obj-$(CONFIG_SDW_GPUCC_MONACO) += gpucc-monaco.o obj-$(CONFIG_SDX_DEBUGCC_LEMUR) += debugcc-sdxlemur.o obj-$(CONFIG_SDX_DEBUGCC_NIGHTJAR) += debugcc-sdxnightjar.o obj-$(CONFIG_SDX_GCC_LEMUR) += gcc-sdxlemur.o obj-$(CONFIG_SDX_GCC_NIGHTJAR) += gcc-sdxnightjar.o obj-$(CONFIG_SDW_GCC_MONACO) += gcc-monaco.o obj-$(CONFIG_SDW_GPUCC_MONACO) += gpucc-monaco.o obj-$(CONFIG_SM_CAMCC_6150) += camcc-sm6150.o obj-$(CONFIG_SM_CAMCC_8150) += camcc-sm8150.o obj-$(CONFIG_SM_CAMCC_SHIMA) += camcc-shima.o Loading drivers/clk/qcom/dispcc-monaco.c 0 → 100644 +588 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. */ #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of_device.h> #include <linux/of.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,dispcc-monaco.h> #include "clk-alpha-pll.h" #include "clk-branch.h" #include "clk-rcg.h" #include "clk-regmap-divider.h" #include "common.h" #include "vdd-level-monaco.h" static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NOMINAL + 1, 1, vdd_corner); static struct clk_vdd_class *disp_cc_monaco_regulators[] = { &vdd_cx, }; enum { P_BI_TCXO, P_DSI0_PHY_PLL_OUT_BYTECLK, P_DSI0_PHY_PLL_OUT_DSICLK, P_DSI1_PHY_PLL_OUT_DSICLK, P_GPLL0_OUT_MAIN, P_SLEEP_CLK, }; static const struct parent_map disp_cc_parent_map_0[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_MAIN, 4 }, }; static const struct clk_parent_data disp_cc_parent_data_0[] = { { .fw_name = "bi_tcxo", }, { .fw_name = "gpll0_out_main" }, }; static const struct parent_map disp_cc_parent_map_1[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, }; static const struct clk_parent_data disp_cc_parent_data_1[] = { { .fw_name = "bi_tcxo", }, { .fw_name = "dsi0_phy_pll_out_byteclk", .name = "dsi0_phy_pll_out_byteclk" }, }; static const struct parent_map disp_cc_parent_map_2[] = { { P_BI_TCXO, 0 }, }; static const struct clk_parent_data disp_cc_parent_data_2[] = { { .fw_name = "bi_tcxo", }, }; static const struct clk_parent_data disp_cc_parent_data_2_ao[] = { { .fw_name = "bi_tcxo_ao", }, }; static const struct parent_map disp_cc_parent_map_3[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, }; static const struct clk_parent_data disp_cc_parent_data_3[] = { { .fw_name = "bi_tcxo" }, { .fw_name = "dsi0_phy_pll_out_dsiclk", .name = "dsi0_phy_pll_out_dsiclk" }, { .fw_name = "dsi1_phy_pll_out_dsiclk", .name = "dsi1_phy_pll_out_dsiclk" }, }; static const struct parent_map disp_cc_parent_map_4[] = { { P_SLEEP_CLK, 0 }, }; static const struct clk_parent_data disp_cc_parent_data_4[] = { { .fw_name = "sleep_clk" }, }; static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), { } }; static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { .cmd_rcgr = 0x2154, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_0, .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_ahb_clk_src", .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 19200000, [VDD_LOW] = 37500000, [VDD_NOMINAL] = 75000000}, }, }; static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { .cmd_rcgr = 0x20a4, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_1, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk_src", .parent_data = disp_cc_parent_data_1, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, .ops = &clk_byte2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 187500000, [VDD_LOW] = 300000000, [VDD_NOMINAL] = 358000000}, }, }; static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), { } }; static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { .cmd_rcgr = 0x20c0, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_1, .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk_src", .parent_data = disp_cc_parent_data_1, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 19200000}, }, }; static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), { } }; static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { .cmd_rcgr = 0x2074, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_0, .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk_src", .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 200000000, [VDD_LOW] = 300000000, [VDD_NOMINAL] = 400000000}, }, }; static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { .cmd_rcgr = 0x205c, .mnd_width = 8, .hid_width = 5, .parent_map = disp_cc_parent_map_3, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, .ops = &clk_pixel_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 328125000, [VDD_LOW] = 525000000, [VDD_NOMINAL] = 625000000}, }, }; static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { .cmd_rcgr = 0x208c, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_2, .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk_src", .parent_data = disp_cc_parent_data_2, .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 19200000}, }, }; static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { F(32000, P_SLEEP_CLK, 1, 0, 0), { } }; static struct clk_rcg2 disp_cc_sleep_clk_src = { .cmd_rcgr = 0x6050, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_4, .freq_tbl = ftbl_disp_cc_sleep_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_sleep_clk_src", .parent_data = disp_cc_parent_data_4, .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 32000}, }, }; static struct clk_rcg2 disp_cc_xo_clk_src = { .cmd_rcgr = 0x6034, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_2, .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_xo_clk_src", .parent_data = disp_cc_parent_data_2_ao, .num_parents = ARRAY_SIZE(disp_cc_parent_data_2_ao), .ops = &clk_rcg2_ops, }, }; static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { .reg = 0x20bc, .shift = 0, .width = 4, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_byte0_div_clk_src", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_GET_RATE_NOCACHE, .ops = &clk_regmap_div_ops, }, }; static struct clk_branch disp_cc_mdss_ahb_clk = { .halt_reg = 0x2044, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2044, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_ahb_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_byte0_clk = { .halt_reg = 0x201c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x201c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_byte0_intf_clk = { .halt_reg = 0x2020, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2020, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_intf_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_esc0_clk = { .halt_reg = 0x2024, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2024, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_esc0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_mdp_clk = { .halt_reg = 0x2008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_mdp_lut_clk = { .halt_reg = 0x2010, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x2010, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_lut_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { .halt_reg = 0x4004, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x4004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_non_gdsc_ahb_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_pclk0_clk = { .halt_reg = 0x2004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_vsync_clk = { .halt_reg = 0x2018, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2018, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_sleep_clk = { .halt_reg = 0x6068, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x6068, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_sleep_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_sleep_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_xo_clk = { .halt_reg = 0x604c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x604c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_xo_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_xo_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_regmap *disp_cc_monaco_clocks[] = { [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr, [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr, [DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr, [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr, }; static const struct regmap_config disp_cc_monaco_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x10000, .fast_io = true, }; static const struct qcom_cc_desc disp_cc_monaco_desc = { .config = &disp_cc_monaco_regmap_config, .clks = disp_cc_monaco_clocks, .num_clks = ARRAY_SIZE(disp_cc_monaco_clocks), .clk_regulators = disp_cc_monaco_regulators, .num_clk_regulators = ARRAY_SIZE(disp_cc_monaco_regulators), }; static const struct of_device_id disp_cc_monaco_match_table[] = { { .compatible = "qcom,monaco-dispcc" }, { } }; MODULE_DEVICE_TABLE(of, disp_cc_monaco_match_table); static int disp_cc_monaco_probe(struct platform_device *pdev) { int ret; ret = qcom_cc_probe(pdev, &disp_cc_monaco_desc); if (ret) { dev_err(&pdev->dev, "Failed to register DISP CC clocks\n"); return ret; } dev_info(&pdev->dev, "Registered DISP CC clocks\n"); return ret; } static void disp_cc_monaco_sync_state(struct device *dev) { qcom_cc_sync_state(dev, &disp_cc_monaco_desc); } static struct platform_driver disp_cc_monaco_driver = { .probe = disp_cc_monaco_probe, .driver = { .name = "disp_cc-monaco", .of_match_table = disp_cc_monaco_match_table, .sync_state = disp_cc_monaco_sync_state, }, }; static int __init disp_cc_monaco_init(void) { return platform_driver_register(&disp_cc_monaco_driver); } subsys_initcall(disp_cc_monaco_init); static void __exit disp_cc_monaco_exit(void) { platform_driver_unregister(&disp_cc_monaco_driver); } module_exit(disp_cc_monaco_exit); MODULE_DESCRIPTION("QTI DISP_CC MONACO Driver"); MODULE_LICENSE("GPL v2"); Loading
drivers/clk/qcom/Kconfig +9 −0 Original line number Diff line number Diff line Loading @@ -793,6 +793,15 @@ config SA_DEBUGCC_DIREWOLF Say Y if you want to support the debug clocks such as clock measurement functionality. config SDW_DISPCC_MONACO tristate "MONACO Display Clock Controller" depends on SDW_GCC_MONACO help Support for the display clock controller on Qualcomm Technologies, Inc. MONACO devices. Say Y if you want to support display devices and functionality such as splash screen. endif config VIRTIO_CLK Loading
drivers/clk/qcom/Makefile +3 −2 Original line number Diff line number Diff line Loading @@ -69,12 +69,13 @@ obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o obj-$(CONFIG_SDW_DISPCC_MONACO) += dispcc-monaco.o obj-$(CONFIG_SDW_GCC_MONACO) += gcc-monaco.o obj-$(CONFIG_SDW_GPUCC_MONACO) += gpucc-monaco.o obj-$(CONFIG_SDX_DEBUGCC_LEMUR) += debugcc-sdxlemur.o obj-$(CONFIG_SDX_DEBUGCC_NIGHTJAR) += debugcc-sdxnightjar.o obj-$(CONFIG_SDX_GCC_LEMUR) += gcc-sdxlemur.o obj-$(CONFIG_SDX_GCC_NIGHTJAR) += gcc-sdxnightjar.o obj-$(CONFIG_SDW_GCC_MONACO) += gcc-monaco.o obj-$(CONFIG_SDW_GPUCC_MONACO) += gpucc-monaco.o obj-$(CONFIG_SM_CAMCC_6150) += camcc-sm6150.o obj-$(CONFIG_SM_CAMCC_8150) += camcc-sm8150.o obj-$(CONFIG_SM_CAMCC_SHIMA) += camcc-shima.o Loading
drivers/clk/qcom/dispcc-monaco.c 0 → 100644 +588 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. */ #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of_device.h> #include <linux/of.h> #include <linux/regmap.h> #include <dt-bindings/clock/qcom,dispcc-monaco.h> #include "clk-alpha-pll.h" #include "clk-branch.h" #include "clk-rcg.h" #include "clk-regmap-divider.h" #include "common.h" #include "vdd-level-monaco.h" static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NOMINAL + 1, 1, vdd_corner); static struct clk_vdd_class *disp_cc_monaco_regulators[] = { &vdd_cx, }; enum { P_BI_TCXO, P_DSI0_PHY_PLL_OUT_BYTECLK, P_DSI0_PHY_PLL_OUT_DSICLK, P_DSI1_PHY_PLL_OUT_DSICLK, P_GPLL0_OUT_MAIN, P_SLEEP_CLK, }; static const struct parent_map disp_cc_parent_map_0[] = { { P_BI_TCXO, 0 }, { P_GPLL0_OUT_MAIN, 4 }, }; static const struct clk_parent_data disp_cc_parent_data_0[] = { { .fw_name = "bi_tcxo", }, { .fw_name = "gpll0_out_main" }, }; static const struct parent_map disp_cc_parent_map_1[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, }; static const struct clk_parent_data disp_cc_parent_data_1[] = { { .fw_name = "bi_tcxo", }, { .fw_name = "dsi0_phy_pll_out_byteclk", .name = "dsi0_phy_pll_out_byteclk" }, }; static const struct parent_map disp_cc_parent_map_2[] = { { P_BI_TCXO, 0 }, }; static const struct clk_parent_data disp_cc_parent_data_2[] = { { .fw_name = "bi_tcxo", }, }; static const struct clk_parent_data disp_cc_parent_data_2_ao[] = { { .fw_name = "bi_tcxo_ao", }, }; static const struct parent_map disp_cc_parent_map_3[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, }; static const struct clk_parent_data disp_cc_parent_data_3[] = { { .fw_name = "bi_tcxo" }, { .fw_name = "dsi0_phy_pll_out_dsiclk", .name = "dsi0_phy_pll_out_dsiclk" }, { .fw_name = "dsi1_phy_pll_out_dsiclk", .name = "dsi1_phy_pll_out_dsiclk" }, }; static const struct parent_map disp_cc_parent_map_4[] = { { P_SLEEP_CLK, 0 }, }; static const struct clk_parent_data disp_cc_parent_data_4[] = { { .fw_name = "sleep_clk" }, }; static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), { } }; static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { .cmd_rcgr = 0x2154, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_0, .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_ahb_clk_src", .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 19200000, [VDD_LOW] = 37500000, [VDD_NOMINAL] = 75000000}, }, }; static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { .cmd_rcgr = 0x20a4, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_1, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk_src", .parent_data = disp_cc_parent_data_1, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, .ops = &clk_byte2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 187500000, [VDD_LOW] = 300000000, [VDD_NOMINAL] = 358000000}, }, }; static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), { } }; static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { .cmd_rcgr = 0x20c0, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_1, .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk_src", .parent_data = disp_cc_parent_data_1, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 19200000}, }, }; static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), { } }; static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { .cmd_rcgr = 0x2074, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_0, .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk_src", .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 200000000, [VDD_LOW] = 300000000, [VDD_NOMINAL] = 400000000}, }, }; static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { .cmd_rcgr = 0x205c, .mnd_width = 8, .hid_width = 5, .parent_map = disp_cc_parent_map_3, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, .ops = &clk_pixel_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 328125000, [VDD_LOW] = 525000000, [VDD_NOMINAL] = 625000000}, }, }; static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { .cmd_rcgr = 0x208c, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_2, .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk_src", .parent_data = disp_cc_parent_data_2, .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 19200000}, }, }; static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { F(32000, P_SLEEP_CLK, 1, 0, 0), { } }; static struct clk_rcg2 disp_cc_sleep_clk_src = { .cmd_rcgr = 0x6050, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_4, .freq_tbl = ftbl_disp_cc_sleep_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_sleep_clk_src", .parent_data = disp_cc_parent_data_4, .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 32000}, }, }; static struct clk_rcg2 disp_cc_xo_clk_src = { .cmd_rcgr = 0x6034, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_2, .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_xo_clk_src", .parent_data = disp_cc_parent_data_2_ao, .num_parents = ARRAY_SIZE(disp_cc_parent_data_2_ao), .ops = &clk_rcg2_ops, }, }; static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { .reg = 0x20bc, .shift = 0, .width = 4, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_byte0_div_clk_src", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_GET_RATE_NOCACHE, .ops = &clk_regmap_div_ops, }, }; static struct clk_branch disp_cc_mdss_ahb_clk = { .halt_reg = 0x2044, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2044, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_ahb_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_byte0_clk = { .halt_reg = 0x201c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x201c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_byte0_intf_clk = { .halt_reg = 0x2020, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2020, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_intf_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_esc0_clk = { .halt_reg = 0x2024, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2024, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_esc0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_mdp_clk = { .halt_reg = 0x2008, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2008, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_mdp_lut_clk = { .halt_reg = 0x2010, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x2010, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_mdp_lut_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { .halt_reg = 0x4004, .halt_check = BRANCH_HALT_VOTED, .clkr = { .enable_reg = 0x4004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_non_gdsc_ahb_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_pclk0_clk = { .halt_reg = 0x2004, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2004, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_mdss_vsync_clk = { .halt_reg = 0x2018, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x2018, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_sleep_clk = { .halt_reg = 0x6068, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x6068, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_sleep_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_sleep_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch disp_cc_xo_clk = { .halt_reg = 0x604c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x604c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "disp_cc_xo_clk", .parent_data = &(const struct clk_parent_data){ .hw = &disp_cc_xo_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_regmap *disp_cc_monaco_clocks[] = { [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr, [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr, [DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr, [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr, }; static const struct regmap_config disp_cc_monaco_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x10000, .fast_io = true, }; static const struct qcom_cc_desc disp_cc_monaco_desc = { .config = &disp_cc_monaco_regmap_config, .clks = disp_cc_monaco_clocks, .num_clks = ARRAY_SIZE(disp_cc_monaco_clocks), .clk_regulators = disp_cc_monaco_regulators, .num_clk_regulators = ARRAY_SIZE(disp_cc_monaco_regulators), }; static const struct of_device_id disp_cc_monaco_match_table[] = { { .compatible = "qcom,monaco-dispcc" }, { } }; MODULE_DEVICE_TABLE(of, disp_cc_monaco_match_table); static int disp_cc_monaco_probe(struct platform_device *pdev) { int ret; ret = qcom_cc_probe(pdev, &disp_cc_monaco_desc); if (ret) { dev_err(&pdev->dev, "Failed to register DISP CC clocks\n"); return ret; } dev_info(&pdev->dev, "Registered DISP CC clocks\n"); return ret; } static void disp_cc_monaco_sync_state(struct device *dev) { qcom_cc_sync_state(dev, &disp_cc_monaco_desc); } static struct platform_driver disp_cc_monaco_driver = { .probe = disp_cc_monaco_probe, .driver = { .name = "disp_cc-monaco", .of_match_table = disp_cc_monaco_match_table, .sync_state = disp_cc_monaco_sync_state, }, }; static int __init disp_cc_monaco_init(void) { return platform_driver_register(&disp_cc_monaco_driver); } subsys_initcall(disp_cc_monaco_init); static void __exit disp_cc_monaco_exit(void) { platform_driver_unregister(&disp_cc_monaco_driver); } module_exit(disp_cc_monaco_exit); MODULE_DESCRIPTION("QTI DISP_CC MONACO Driver"); MODULE_LICENSE("GPL v2");
