Loading drivers/clk/qcom/gcc-shima.c +2 −0 Original line number Diff line number Diff line Loading @@ -1861,6 +1861,7 @@ static struct clk_branch gcc_gpu_memnoc_gfx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_memnoc_gfx_clk", .flags = CLK_DONT_HOLD_STATE, .ops = &clk_branch2_aon_ops, }, }, Loading @@ -1874,6 +1875,7 @@ static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_snoc_dvm_gfx_clk", .flags = CLK_DONT_HOLD_STATE, .ops = &clk_branch2_aon_ops, }, }, Loading drivers/clk/qcom/gpucc-shima.c +3 −2 Original line number Diff line number Diff line Loading @@ -306,7 +306,7 @@ static struct clk_branch gpu_cc_cx_gmu_clk = { .hw = &gpu_cc_gmu_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT | CLK_DONT_HOLD_STATE, .ops = &clk_branch2_aon_ops, }, }, Loading Loading @@ -346,6 +346,7 @@ static struct clk_branch gpu_cc_cxo_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cxo_clk", .flags = CLK_DONT_HOLD_STATE, .ops = &clk_branch2_aon_ops, }, }, Loading Loading @@ -412,7 +413,7 @@ static struct clk_branch gpu_cc_hub_cx_int_clk = { .hw = &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT | CLK_DONT_HOLD_STATE, .ops = &clk_branch2_aon_ops, }, }, Loading Loading
drivers/clk/qcom/gcc-shima.c +2 −0 Original line number Diff line number Diff line Loading @@ -1861,6 +1861,7 @@ static struct clk_branch gcc_gpu_memnoc_gfx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_memnoc_gfx_clk", .flags = CLK_DONT_HOLD_STATE, .ops = &clk_branch2_aon_ops, }, }, Loading @@ -1874,6 +1875,7 @@ static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gpu_snoc_dvm_gfx_clk", .flags = CLK_DONT_HOLD_STATE, .ops = &clk_branch2_aon_ops, }, }, Loading
drivers/clk/qcom/gpucc-shima.c +3 −2 Original line number Diff line number Diff line Loading @@ -306,7 +306,7 @@ static struct clk_branch gpu_cc_cx_gmu_clk = { .hw = &gpu_cc_gmu_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT | CLK_DONT_HOLD_STATE, .ops = &clk_branch2_aon_ops, }, }, Loading Loading @@ -346,6 +346,7 @@ static struct clk_branch gpu_cc_cxo_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpu_cc_cxo_clk", .flags = CLK_DONT_HOLD_STATE, .ops = &clk_branch2_aon_ops, }, }, Loading Loading @@ -412,7 +413,7 @@ static struct clk_branch gpu_cc_hub_cx_int_clk = { .hw = &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT | CLK_DONT_HOLD_STATE, .ops = &clk_branch2_aon_ops, }, }, Loading