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Commit c6ad1158 authored by Ben Dooks's avatar Ben Dooks
Browse files

Merge branch 'next-s3c24xx' into next-merged

parents 1d19fdba 28ab44c5

arch/arm/mach-s3c2410/Kconfig

+2 −5
Original line number Diff line number Diff line
@@ -33,11 +33,6 @@ config S3C2410_GPIO 
	help

	  GPIO code for S3C2410 and similar processors



config S3C2410_CLOCK

	bool

	help

	  Clock code for the S3C2410, and similar processors



config SIMTEC_NOR

	bool

	help
@@ -85,6 +80,7 @@ config ARCH_BAST 
	select PM_SIMTEC if PM

	select SIMTEC_NOR

	select MACH_BAST_IDE

	select S3C24XX_DCLK

	select ISA

	help

	  Say Y here if you are using the Simtec Electronics EB2410ITX
@@ -122,6 +118,7 @@ config MACH_TCT_HAMMER 
config MACH_VR1000

	bool "Thorcom VR1000"

	select PM_SIMTEC if PM

	select S3C24XX_DCLK

	select SIMTEC_NOR

	select MACH_BAST_IDE

	select CPU_S3C2410

arch/arm/mach-s3c2410/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -15,7 +15,6 @@ obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o 
obj-$(CONFIG_CPU_S3C2410_DMA)	+= dma.o

obj-$(CONFIG_S3C2410_PM)	+= pm.o sleep.o

obj-$(CONFIG_S3C2410_GPIO)	+= gpio.o

obj-$(CONFIG_S3C2410_CLOCK)	+= clock.o



# Machine support

arch/arm/mach-s3c2410/include/mach/regs-clock.h

+0 −33
Original line number Diff line number Diff line
@@ -42,13 +42,6 @@ 
#define S3C2410_CLKCON_IIS	     (1<<17)

#define S3C2410_CLKCON_SPI	     (1<<18)



#define S3C2410_PLLCON_MDIVSHIFT     12

#define S3C2410_PLLCON_PDIVSHIFT     4

#define S3C2410_PLLCON_SDIVSHIFT     0

#define S3C2410_PLLCON_MDIVMASK	     ((1<<(1+(19-12)))-1)

#define S3C2410_PLLCON_PDIVMASK	     ((1<<5)-1)

#define S3C2410_PLLCON_SDIVMASK	     3



/* DCLKCON register addresses in gpio.h */



#define S3C2410_DCLKCON_DCLK0EN	     (1<<0)
@@ -76,32 +69,6 @@ 
#define S3C2410_CLKSLOW_SLOWVAL(x)	(x)

#define S3C2410_CLKSLOW_GET_SLOWVAL(x)	((x) & 7)



#ifndef __ASSEMBLY__



#include <asm/div64.h>



static inline unsigned int

s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)

{

	unsigned int mdiv, pdiv, sdiv;

	uint64_t fvco;



	mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;

	pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;

	sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;



	mdiv &= S3C2410_PLLCON_MDIVMASK;

	pdiv &= S3C2410_PLLCON_PDIVMASK;

	sdiv &= S3C2410_PLLCON_SDIVMASK;



	fvco = (uint64_t)baseclk * (mdiv + 8);

	do_div(fvco, (pdiv + 2) << sdiv);



	return (unsigned int)fvco;

}



#endif /* __ASSEMBLY__ */



#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)



/* extra registers */

arch/arm/mach-s3c2410/include/mach/regs-gpio.h

+0 −7
Original line number Diff line number Diff line
@@ -1053,13 +1053,6 @@ 
#define S3C24XX_EXTINT1	   S3C24XX_GPIOREG2(0x8C)

#define S3C24XX_EXTINT2	   S3C24XX_GPIOREG2(0x90)



/* values for S3C2410_EXTINT0/1/2 */

#define S3C2410_EXTINT_LOWLEV	 (0x00)

#define S3C2410_EXTINT_HILEV	 (0x01)

#define S3C2410_EXTINT_FALLEDGE	 (0x02)

#define S3C2410_EXTINT_RISEEDGE	 (0x04)

#define S3C2410_EXTINT_BOTHEDGE	 (0x06)



/* interrupt filtering conrrol for EINT16..EINT23 */

#define S3C2410_EINFLT0	   S3C2410_GPIOREG(0x94)

#define S3C2410_EINFLT1	   S3C2410_GPIOREG(0x98)

arch/arm/mach-s3c2410/include/mach/spi.h

+7 −0
Original line number Diff line number Diff line
@@ -22,5 +22,12 @@ struct s3c2410_spi_info { 
	void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);

};



/* Standard setup / suspend routines for SPI GPIO pins. */



extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,

						 int enable);



extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,

					      int enable);



#endif /* __ASM_ARCH_SPI_H */