crypto: cavium - Add the Virtual Function driver for CPT (c694b233) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/crypto/cavium/cpt/Makefile

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		obj-$(CONFIG_CAVIUM_CPT) += cptpf.o
		obj-$(CONFIG_CAVIUM_CPT) += cptpf.o cptvf.o
		cptpf-objs := cptpf_main.o cptpf_mbox.o
		cptvf-objs := cptvf_main.o cptvf_reqmanager.o cptvf_mbox.o cptvf_algs.o

drivers/crypto/cavium/cpt/cptvf.h

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		/*
		* Copyright (C) 2016 Cavium, Inc.
		*
		* This program is free software; you can redistribute it and/or modify it
		* under the terms of version 2 of the GNU General Public License
		* as published by the Free Software Foundation.
		*/

		#ifndef __CPTVF_H
		#define __CPTVF_H

		#include <linux/list.h>
		#include "cpt_common.h"

		/* Default command queue length */
		#define CPT_CMD_QLEN 2046
		#define CPT_CMD_QCHUNK_SIZE 1023

		/* Default command timeout in seconds */
		#define CPT_COMMAND_TIMEOUT 4
		#define CPT_TIMER_THOLD 0xFFFF
		#define CPT_NUM_QS_PER_VF 1
		#define CPT_INST_SIZE 64
		#define CPT_NEXT_CHUNK_PTR_SIZE 8

		#define CPT_VF_MSIX_VECTORS 2
		#define CPT_VF_INTR_MBOX_MASK BIT(0)
		#define CPT_VF_INTR_DOVF_MASK BIT(1)
		#define CPT_VF_INTR_IRDE_MASK BIT(2)
		#define CPT_VF_INTR_NWRP_MASK BIT(3)
		#define CPT_VF_INTR_SERR_MASK BIT(4)
		#define DMA_DIRECT_DIRECT 0 /* Input DIRECT, Output DIRECT */
		#define DMA_GATHER_SCATTER 1
		#define FROM_DPTR 1

		/**
		* Enumeration cpt_vf_int_vec_e
		*
		* CPT VF MSI-X Vector Enumeration
		* Enumerates the MSI-X interrupt vectors.
		*/
		enum cpt_vf_int_vec_e {
		CPT_VF_INT_VEC_E_MISC = 0x00,
		CPT_VF_INT_VEC_E_DONE = 0x01
		};

		struct command_chunk {
		u8 *head;
		dma_addr_t dma_addr;
		u32 size; /* Chunk size, max CPT_INST_CHUNK_MAX_SIZE */
		struct hlist_node nextchunk;
		};

		struct command_queue {
		spinlock_t lock; /* command queue lock */
		u32 idx; /* Command queue host write idx */
		u32 nchunks; /* Number of command chunks */
		struct command_chunk qhead; / Command queue head, instructions
		* are inserted here
		*/
		struct hlist_head chead;
		};

		struct command_qinfo {
		u32 cmd_size;
		u32 qchunksize; /* Command queue chunk size */
		struct command_queue queue[CPT_NUM_QS_PER_VF];
		};

		struct pending_entry {
		u8 busy; /* Entry status (free/busy) */

		volatile u64 completion_addr; / Completion address */
		void *post_arg;
		void (callback)(int, void ); /* Kernel ASYNC request callabck */
		void callback_arg; / Kernel ASYNC request callabck arg */
		};

		struct pending_queue {
		struct pending_entry head; / head of the queue */
		u32 front; /* Process work from here */
		u32 rear; /* Append new work here */
		atomic64_t pending_count;
		spinlock_t lock; /* Queue lock */
		};

		struct pending_qinfo {
		u32 nr_queues; /* Number of queues supported */
		u32 qlen; /* Queue length */
		struct pending_queue queue[CPT_NUM_QS_PER_VF];
		};

		#define for_each_pending_queue(qinfo, q, i) \
		for (i = 0, q = &qinfo->queue[i]; i < qinfo->nr_queues; i++, \
		q = &qinfo->queue[i])

		struct cpt_vf {
		u16 flags; /* Flags to hold device status bits */
		u8 vfid; /* Device Index 0...CPT_MAX_VF_NUM */
		u8 vftype; /* VF type of SE_TYPE(1) or AE_TYPE(1) */
		u8 vfgrp; /* VF group (0 - 8) */
		u8 node; /* Operating node: Bits (46:44) in BAR0 address */
		u8 priority; /* VF priority ring: 1-High proirity round
		* robin ring;0-Low priority round robin ring;
		*/
		struct pci_dev pdev; / pci device handle */
		void __iomem reg_base; / Register start address */
		void wqe_info; / BH worker info */
		/* MSI-X */
		bool msix_enabled;
		struct msix_entry msix_entries[CPT_VF_MSIX_VECTORS];
		bool irq_allocated[CPT_VF_MSIX_VECTORS];
		cpumask_var_t affinity_mask[CPT_VF_MSIX_VECTORS];
		/* Command and Pending queues */
		u32 qsize;
		u32 nr_queues;
		struct command_qinfo cqinfo; /* Command queue information */
		struct pending_qinfo pqinfo; /* Pending queue information */
		/* VF-PF mailbox communication */
		bool pf_acked;
		bool pf_nacked;
		};

		int cptvf_send_vf_up(struct cpt_vf *cptvf);
		int cptvf_send_vf_down(struct cpt_vf *cptvf);
		int cptvf_send_vf_to_grp_msg(struct cpt_vf *cptvf);
		int cptvf_send_vf_priority_msg(struct cpt_vf *cptvf);
		int cptvf_send_vq_size_msg(struct cpt_vf *cptvf);
		int cptvf_check_pf_ready(struct cpt_vf *cptvf);
		void cptvf_handle_mbox_intr(struct cpt_vf *cptvf);
		void cvm_crypto_exit(void);
		int cvm_crypto_init(struct cpt_vf *cptvf);
		void vq_post_process(struct cpt_vf *cptvf, u32 qno);
		void cptvf_write_vq_doorbell(struct cpt_vf *cptvf, u32 val);
		#endif /* __CPTVF_H */

drivers/crypto/cavium/cpt/cptvf_algs.c

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		/*
		* Copyright (C) 2016 Cavium, Inc.
		*
		* This program is free software; you can redistribute it and/or modify it
		* under the terms of version 2 of the GNU General Public License
		* as published by the Free Software Foundation.
		*/

		#include <crypto/aes.h>
		#include <crypto/algapi.h>
		#include <crypto/authenc.h>
		#include <crypto/cryptd.h>
		#include <crypto/crypto_wq.h>
		#include <crypto/des.h>
		#include <crypto/xts.h>
		#include <linux/crypto.h>
		#include <linux/err.h>
		#include <linux/list.h>
		#include <linux/scatterlist.h>

		#include "cptvf.h"
		#include "cptvf_algs.h"

		struct cpt_device_handle {
		void *cdev[MAX_DEVICES];
		u32 dev_count;
		};

		static struct cpt_device_handle dev_handle;

		static void cvm_callback(u32 status, void *arg)
		{
		struct crypto_async_request req = (struct crypto_async_request )arg;

		req->complete(req, !status);
		}

		static inline void update_input_iv(struct cpt_request_info *req_info,
		u8 *iv, u32 enc_iv_len,
		u32 *argcnt)
		{
		/* Setting the iv information */
		req_info->in[argcnt].vptr = (void )iv;
		req_info->in[*argcnt].size = enc_iv_len;
		req_info->req.dlen += enc_iv_len;

		++(*argcnt);
		}

		static inline void update_output_iv(struct cpt_request_info *req_info,
		u8 *iv, u32 enc_iv_len,
		u32 *argcnt)
		{
		/* Setting the iv information */
		req_info->out[argcnt].vptr = (void )iv;
		req_info->out[*argcnt].size = enc_iv_len;
		req_info->rlen += enc_iv_len;

		++(*argcnt);
		}

		static inline void update_input_data(struct cpt_request_info *req_info,
		struct scatterlist *inp_sg,
		u32 nbytes, u32 *argcnt)
		{
		req_info->req.dlen += nbytes;

		while (nbytes) {
		u32 len = min(nbytes, inp_sg->length);
		u8 *ptr = sg_virt(inp_sg);

		req_info->in[argcnt].vptr = (void )ptr;
		req_info->in[*argcnt].size = len;
		nbytes -= len;

		++(*argcnt);
		++inp_sg;
		}
		}

		static inline void update_output_data(struct cpt_request_info *req_info,
		struct scatterlist *outp_sg,
		u32 nbytes, u32 *argcnt)
		{
		req_info->rlen += nbytes;

		while (nbytes) {
		u32 len = min(nbytes, outp_sg->length);
		u8 *ptr = sg_virt(outp_sg);

		req_info->out[argcnt].vptr = (void )ptr;
		req_info->out[*argcnt].size = len;
		nbytes -= len;
		++(*argcnt);
		++outp_sg;
		}
		}

		static inline u32 create_ctx_hdr(struct ablkcipher_request *req, u32 enc,
		u32 cipher_type, u32 aes_key_type,
		u32 *argcnt)
		{
		struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
		struct cvm_enc_ctx *ctx = crypto_ablkcipher_ctx(tfm);
		struct cvm_req_ctx *rctx = ablkcipher_request_ctx(req);
		struct fc_context *fctx = &rctx->fctx;
		u64 *offset_control = &rctx->control_word;
		u32 enc_iv_len = crypto_ablkcipher_ivsize(tfm);
		struct cpt_request_info *req_info = &rctx->cpt_req;
		u64 *ctrl_flags = NULL;

		req_info->ctrl.s.grp = 0;
		req_info->ctrl.s.dma_mode = DMA_GATHER_SCATTER;
		req_info->ctrl.s.se_req = SE_CORE_REQ;

		req_info->req.opcode.s.major = MAJOR_OP_FC \|
		DMA_MODE_FLAG(DMA_GATHER_SCATTER);
		if (enc)
		req_info->req.opcode.s.minor = 2;
		else
		req_info->req.opcode.s.minor = 3;

		req_info->req.param1 = req->nbytes; /* Encryption Data length */
		req_info->req.param2 = 0; /Auth data length /

		fctx->enc.enc_ctrl.e.enc_cipher = cipher_type;
		fctx->enc.enc_ctrl.e.aes_key = aes_key_type;
		fctx->enc.enc_ctrl.e.iv_source = FROM_DPTR;

		if (cipher_type == AES_XTS)
		memcpy(fctx->enc.encr_key, ctx->enc_key, ctx->key_len * 2);
		else
		memcpy(fctx->enc.encr_key, ctx->enc_key, ctx->key_len);
		ctrl_flags = (u64 *)&fctx->enc.enc_ctrl.flags;
		ctrl_flags = cpu_to_be64(ctrl_flags);

		*offset_control = cpu_to_be64(((u64)(enc_iv_len) << 16));
		/* Storing Packet Data Information in offset
		* Control Word First 8 bytes
		*/
		req_info->in[argcnt].vptr = (u8 )offset_control;
		req_info->in[*argcnt].size = CONTROL_WORD_LEN;
		req_info->req.dlen += CONTROL_WORD_LEN;
		++(*argcnt);

		req_info->in[argcnt].vptr = (u8 )fctx;
		req_info->in[*argcnt].size = sizeof(struct fc_context);
		req_info->req.dlen += sizeof(struct fc_context);

		++(*argcnt);

		return 0;
		}

		static inline u32 create_input_list(struct ablkcipher_request *req, u32 enc,
		u32 cipher_type, u32 aes_key_type,
		u32 enc_iv_len)
		{
		struct cvm_req_ctx *rctx = ablkcipher_request_ctx(req);
		struct cpt_request_info *req_info = &rctx->cpt_req;
		u32 argcnt = 0;

		create_ctx_hdr(req, enc, cipher_type, aes_key_type, &argcnt);
		update_input_iv(req_info, req->info, enc_iv_len, &argcnt);
		update_input_data(req_info, req->src, req->nbytes, &argcnt);
		req_info->incnt = argcnt;

		return 0;
		}

		static inline void store_cb_info(struct ablkcipher_request *req,
		struct cpt_request_info *req_info)
		{
		req_info->callback = (void *)cvm_callback;
		req_info->callback_arg = (void *)&req->base;
		}

		static inline void create_output_list(struct ablkcipher_request *req,
		u32 cipher_type,
		u32 enc_iv_len)
		{
		struct cvm_req_ctx *rctx = ablkcipher_request_ctx(req);
		struct cpt_request_info *req_info = &rctx->cpt_req;
		u32 argcnt = 0;

		/* OUTPUT Buffer Processing
		* AES encryption/decryption output would be
		* received in the following format
		*
		* ------IV--------\|------ENCRYPTED/DECRYPTED DATA-----\|
		* [ 16 Bytes/ [ Request Enc/Dec/ DATA Len AES CBC ]
		*/
		/* Reading IV information */
		update_output_iv(req_info, req->info, enc_iv_len, &argcnt);
		update_output_data(req_info, req->dst, req->nbytes, &argcnt);
		req_info->outcnt = argcnt;
		}

		static inline int cvm_enc_dec(struct ablkcipher_request *req, u32 enc,
		u32 cipher_type)
		{
		struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
		struct cvm_enc_ctx *ctx = crypto_ablkcipher_ctx(tfm);
		u32 key_type = AES_128_BIT;
		struct cvm_req_ctx *rctx = ablkcipher_request_ctx(req);
		u32 enc_iv_len = crypto_ablkcipher_ivsize(tfm);
		struct fc_context *fctx = &rctx->fctx;
		struct cpt_request_info *req_info = &rctx->cpt_req;
		void *cdev = NULL;
		int status;

		switch (ctx->key_len) {
		case 16:
		key_type = AES_128_BIT;
		break;
		case 24:
		key_type = AES_192_BIT;
		break;
		case 32:
		if (cipher_type == AES_XTS)
		key_type = AES_128_BIT;
		else
		key_type = AES_256_BIT;
		break;
		case 64:
		if (cipher_type == AES_XTS)
		key_type = AES_256_BIT;
		else
		return -EINVAL;
		break;
		default:
		return -EINVAL;
		}

		if (cipher_type == DES3_CBC)
		key_type = 0;

		memset(req_info, 0, sizeof(struct cpt_request_info));
		memset(fctx, 0, sizeof(struct fc_context));
		create_input_list(req, enc, cipher_type, key_type, enc_iv_len);
		create_output_list(req, cipher_type, enc_iv_len);
		store_cb_info(req, req_info);
		cdev = dev_handle.cdev[smp_processor_id()];
		status = cptvf_do_request(cdev, req_info);
		/* We perform an asynchronous send and once
		* the request is completed the driver would
		* intimate through registered call back functions
		*/

		if (status)
		return status;
		else
		return -EINPROGRESS;
		}

		int cvm_des3_encrypt_cbc(struct ablkcipher_request *req)
		{
		return cvm_enc_dec(req, true, DES3_CBC);
		}

		int cvm_des3_decrypt_cbc(struct ablkcipher_request *req)
		{
		return cvm_enc_dec(req, false, DES3_CBC);
		}

		int cvm_aes_encrypt_xts(struct ablkcipher_request *req)
		{
		return cvm_enc_dec(req, true, AES_XTS);
		}

		int cvm_aes_decrypt_xts(struct ablkcipher_request *req)
		{
		return cvm_enc_dec(req, false, AES_XTS);
		}

		int cvm_aes_encrypt_cbc(struct ablkcipher_request *req)
		{
		return cvm_enc_dec(req, true, AES_CBC);
		}

		int cvm_aes_decrypt_cbc(struct ablkcipher_request *req)
		{
		return cvm_enc_dec(req, false, AES_CBC);
		}

		int cvm_xts_setkey(struct crypto_ablkcipher cipher, const u8 key,
		u32 keylen)
		{
		struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
		struct cvm_enc_ctx *ctx = crypto_tfm_ctx(tfm);
		int err;
		const u8 *key1 = key;
		const u8 *key2 = key + (keylen / 2);

		err = xts_check_key(tfm, key, keylen);
		if (err)
		return err;
		ctx->key_len = keylen;
		memcpy(ctx->enc_key, key1, keylen / 2);
		memcpy(ctx->enc_key + KEY2_OFFSET, key2, keylen / 2);

		return 0;
		}

		int cvm_enc_dec_setkey(struct crypto_ablkcipher cipher, const u8 key,
		u32 keylen)
		{
		struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
		struct cvm_enc_ctx *ctx = crypto_tfm_ctx(tfm);

		if ((keylen == 16) \|\| (keylen == 24) \|\| (keylen == 32)) {
		ctx->key_len = keylen;
		memcpy(ctx->enc_key, key, keylen);
		return 0;
		}
		crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);

		return -EINVAL;
		}

		int cvm_enc_dec_init(struct crypto_tfm *tfm)
		{
		struct cvm_enc_ctx *ctx = crypto_tfm_ctx(tfm);

		memset(ctx, 0, sizeof(*ctx));
		tfm->crt_ablkcipher.reqsize = sizeof(struct cvm_req_ctx) +
		sizeof(struct ablkcipher_request);
		/* Additional memory for ablkcipher_request is
		* allocated since the cryptd daemon uses
		* this memory for request_ctx information
		*/

		return 0;
		}

		struct crypto_alg algs[] = { {
		.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER \| CRYPTO_ALG_ASYNC,
		.cra_blocksize = AES_BLOCK_SIZE,
		.cra_ctxsize = sizeof(struct cvm_enc_ctx),
		.cra_alignmask = 7,
		.cra_priority = 4001,
		.cra_name = "xts(aes)",
		.cra_driver_name = "cavium-xts-aes",
		.cra_type = &crypto_ablkcipher_type,
		.cra_u = {
		.ablkcipher = {
		.ivsize = AES_BLOCK_SIZE,
		.min_keysize = 2 * AES_MIN_KEY_SIZE,
		.max_keysize = 2 * AES_MAX_KEY_SIZE,
		.setkey = cvm_xts_setkey,
		.encrypt = cvm_aes_encrypt_xts,
		.decrypt = cvm_aes_decrypt_xts,
		},
		},
		.cra_init = cvm_enc_dec_init,
		.cra_module = THIS_MODULE,
		}, {
		.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER \| CRYPTO_ALG_ASYNC,
		.cra_blocksize = AES_BLOCK_SIZE,
		.cra_ctxsize = sizeof(struct cvm_enc_ctx),
		.cra_alignmask = 7,
		.cra_priority = 4001,
		.cra_name = "cbc(aes)",
		.cra_driver_name = "cavium-cbc-aes",
		.cra_type = &crypto_ablkcipher_type,
		.cra_u = {
		.ablkcipher = {
		.ivsize = AES_BLOCK_SIZE,
		.min_keysize = AES_MIN_KEY_SIZE,
		.max_keysize = AES_MAX_KEY_SIZE,
		.setkey = cvm_enc_dec_setkey,
		.encrypt = cvm_aes_encrypt_cbc,
		.decrypt = cvm_aes_decrypt_cbc,
		},
		},
		.cra_init = cvm_enc_dec_init,
		.cra_module = THIS_MODULE,
		}, {
		.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER \| CRYPTO_ALG_ASYNC,
		.cra_blocksize = DES3_EDE_BLOCK_SIZE,
		.cra_ctxsize = sizeof(struct cvm_des3_ctx),
		.cra_alignmask = 7,
		.cra_priority = 4001,
		.cra_name = "cbc(des3_ede)",
		.cra_driver_name = "cavium-cbc-des3_ede",
		.cra_type = &crypto_ablkcipher_type,
		.cra_u = {
		.ablkcipher = {
		.min_keysize = DES3_EDE_KEY_SIZE,
		.max_keysize = DES3_EDE_KEY_SIZE,
		.ivsize = DES_BLOCK_SIZE,
		.setkey = cvm_enc_dec_setkey,
		.encrypt = cvm_des3_encrypt_cbc,
		.decrypt = cvm_des3_decrypt_cbc,
		},
		},
		.cra_init = cvm_enc_dec_init,
		.cra_module = THIS_MODULE,
		} };

		static inline int cav_register_algs(void)
		{
		int err = 0;

		err = crypto_register_algs(algs, ARRAY_SIZE(algs));
		if (err)
		return err;

		return 0;
		}

		static inline void cav_unregister_algs(void)
		{
		crypto_unregister_algs(algs, ARRAY_SIZE(algs));
		}

		int cvm_crypto_init(struct cpt_vf *cptvf)
		{
		struct pci_dev *pdev = cptvf->pdev;
		u32 dev_count;

		dev_count = dev_handle.dev_count;
		dev_handle.cdev[dev_count] = cptvf;
		dev_handle.dev_count++;

		if (dev_count == 3) {
		if (cav_register_algs()) {
		dev_err(&pdev->dev, "Error in registering crypto algorithms\n");
		return -EINVAL;
		}
		}

		return 0;
		}

		void cvm_crypto_exit(void)
		{
		u32 dev_count;

		dev_count = --dev_handle.dev_count;
		if (!dev_count)
		cav_unregister_algs();
		}

drivers/crypto/cavium/cpt/cptvf_algs.h

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Original line number	Diff line number	Diff line
		/*
		* Copyright (C) 2016 Cavium, Inc.
		*
		* This program is free software; you can redistribute it and/or modify it
		* under the terms of version 2 of the GNU General Public License
		* as published by the Free Software Foundation.
		*/

		#ifndef _CPTVF_ALGS_H_
		#define _CPTVF_ALGS_H_

		#include "request_manager.h"

		#define MAX_DEVICES 16
		#define MAJOR_OP_FC 0x33
		#define MAX_ENC_KEY_SIZE 32
		#define MAX_HASH_KEY_SIZE 64
		#define MAX_KEY_SIZE (MAX_ENC_KEY_SIZE + MAX_HASH_KEY_SIZE)
		#define CONTROL_WORD_LEN 8
		#define KEY2_OFFSET 48

		#define DMA_MODE_FLAG(dma_mode) \
		(((dma_mode) == DMA_GATHER_SCATTER) ? (1 << 7) : 0)

		enum req_type {
		AE_CORE_REQ,
		SE_CORE_REQ,
		};

		enum cipher_type {
		DES3_CBC = 0x1,
		DES3_ECB = 0x2,
		AES_CBC = 0x3,
		AES_ECB = 0x4,
		AES_CFB = 0x5,
		AES_CTR = 0x6,
		AES_GCM = 0x7,
		AES_XTS = 0x8
		};

		enum aes_type {
		AES_128_BIT = 0x1,
		AES_192_BIT = 0x2,
		AES_256_BIT = 0x3
		};

		union encr_ctrl {
		u64 flags;
		struct {
		#if defined(__BIG_ENDIAN_BITFIELD)
		u64 enc_cipher:4;
		u64 reserved1:1;
		u64 aes_key:2;
		u64 iv_source:1;
		u64 hash_type:4;
		u64 reserved2:3;
		u64 auth_input_type:1;
		u64 mac_len:8;
		u64 reserved3:8;
		u64 encr_offset:16;
		u64 iv_offset:8;
		u64 auth_offset:8;
		#else
		u64 auth_offset:8;
		u64 iv_offset:8;
		u64 encr_offset:16;
		u64 reserved3:8;
		u64 mac_len:8;
		u64 auth_input_type:1;
		u64 reserved2:3;
		u64 hash_type:4;
		u64 iv_source:1;
		u64 aes_key:2;
		u64 reserved1:1;
		u64 enc_cipher:4;
		#endif
		} e;
		};

		struct enc_context {
		union encr_ctrl enc_ctrl;
		u8 encr_key[32];
		u8 encr_iv[16];
		};

		struct fchmac_context {
		u8 ipad[64];
		u8 opad[64]; /* or OPAD */
		};

		struct fc_context {
		struct enc_context enc;
		struct fchmac_context hmac;
		};

		struct cvm_enc_ctx {
		u32 key_len;
		u8 enc_key[MAX_KEY_SIZE];
		};

		struct cvm_des3_ctx {
		u32 key_len;
		u8 des3_key[MAX_KEY_SIZE];
		};

		struct cvm_req_ctx {
		struct cpt_request_info cpt_req;
		u64 control_word;
		struct fc_context fctx;
		};

		int cptvf_do_request(void cptvf, struct cpt_request_info req);
		#endif /_CPTVF_ALGS_H_/

drivers/crypto/cavium/cpt/cptvf_main.c

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