drm/nv40: make detection of 0x4097-ful chipsets available everywhere (c693931d) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/gpu/drm/nouveau/nouveau_drv.h

+14 −0

Original line number	Diff line number	Diff line
		@@ -1574,6 +1574,20 @@ nv_match_device(struct drm_device *dev, unsigned device,
		dev->pdev->subsystem_device == sub_device;
		}

		/* returns 1 if device is one of the nv4x using the 0x4497 object class,
		* helpful to determine a number of other hardware features
		*/
		static inline int
		nv44_graph_class(struct drm_device *dev)
		{
		struct drm_nouveau_private *dev_priv = dev->dev_private;

		if ((dev_priv->chipset & 0xf0) == 0x60)
		return 1;

		return !(0x0baf & (1 << (dev_priv->chipset & 0x0f)));
		}

		/* memory type/access flags, do not match hardware values */
		#define NV_MEM_ACCESS_RO 1
		#define NV_MEM_ACCESS_WO 2

drivers/gpu/drm/nouveau/nv40_graph.c

+1 −2

Original line number	Diff line number	Diff line
		@@ -451,8 +451,7 @@ nv40_graph_register(struct drm_device *dev)
		NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */

		/* curie */
		if (dev_priv->chipset >= 0x60 \|\|
		0x00005450 & (1 << (dev_priv->chipset & 0x0f)))
		if (nv44_graph_class(dev))
		NVOBJ_CLASS(dev, 0x4497, GR);
		else
		NVOBJ_CLASS(dev, 0x4097, GR);

drivers/gpu/drm/nouveau/nv40_grctx.c

+5 −16

Original line number	Diff line number	Diff line
		@@ -117,17 +117,6 @@
		* - get vs count from 0x1540
		*/

		static int
		nv40_graph_4097(struct drm_device *dev)
		{
		struct drm_nouveau_private *dev_priv = dev->dev_private;

		if ((dev_priv->chipset & 0xf0) == 0x60)
		return 0;

		return !!(0x0baf & (1 << dev_priv->chipset));
		}

		static int
		nv40_graph_vs_count(struct drm_device *dev)
		{
		@@ -219,7 +208,7 @@ nv40_graph_construct_general(struct nouveau_grctx *ctx)
		gr_def(ctx, 0x4009dc, 0x80000000);
		} else {
		cp_ctx(ctx, 0x400840, 20);
		if (!nv40_graph_4097(ctx->dev)) {
		if (nv44_graph_class(ctx->dev)) {
		for (i = 0; i < 8; i++)
		gr_def(ctx, 0x400860 + (i * 4), 0x00000001);
		}
		@@ -228,7 +217,7 @@ nv40_graph_construct_general(struct nouveau_grctx *ctx)
		gr_def(ctx, 0x400888, 0x00000040);
		cp_ctx(ctx, 0x400894, 11);
		gr_def(ctx, 0x400894, 0x00000040);
		if (nv40_graph_4097(ctx->dev)) {
		if (!nv44_graph_class(ctx->dev)) {
		for (i = 0; i < 8; i++)
		gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000);
		}
		@@ -546,7 +535,7 @@ nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx)
		static void
		nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx)
		{
		int len = nv40_graph_4097(ctx->dev) ? 0x0684 : 0x0084;
		int len = nv44_graph_class(ctx->dev) ? 0x0084 : 0x0684;

		cp_out (ctx, 0x300000);
		cp_lsr (ctx, len - 4);
		@@ -582,11 +571,11 @@ nv40_graph_construct_shader(struct nouveau_grctx *ctx)
		} else {
		b0_offset = 0x1d40/4; /* 2200 */
		b1_offset = 0x3f40/4; /* 0b00 : 0a40 */
		vs_len = nv40_graph_4097(dev) ? 0x4a40/4 : 0x4980/4;
		vs_len = nv44_graph_class(dev) ? 0x4980/4 : 0x4a40/4;
		}

		cp_lsr(ctx, vs_len * vs_nr + 0x300/4);
		cp_out(ctx, nv40_graph_4097(dev) ? 0x800041 : 0x800029);
		cp_out(ctx, nv44_graph_class(dev) ? 0x800029 : 0x800041);

		offset = ctx->ctxvals_pos;
		ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len));