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Commit c6617edf authored by Robin Murphy's avatar Robin Murphy Committed by Matthias Maennich
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BACKPORT: arm64: perf: Support new DT compatibles 



Add support for matching the new PMUs. For now, this just wires them up
as generic PMUv3 such that people writing DTs for new SoCs can do the
right thing, and at least have architectural and raw events be usable.
We can come back and fill in event maps for sysfs and/or perf tools at
a later date.

Change-Id: I0c0839f6fff87934e97708176f783514bdee7f58
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarRobin Murphy <robin.murphy@arm.com>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
(cherry picked from commit 29cc4ceeac1274ab8363a11b81ebd99f3b023985
 git://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git for-next/perf)

Bug: 176519087
Link: https://lore.kernel.org/linux-arm-kernel/20200225190125.GA2781@bogus/T/#mdaa003324f263cc9541d412f7ba6b9519d6603fe


Signed-off-by: default avatarChun-Hung Wu <chun-hung.wu@mediatek.com>
Change-Id: I335d4c9a9bfcfcfeb18b096cfe660209d3b62820
parent b227e978

arch/arm64/kernel/perf_event.c

+77 −91
Original line number Diff line number Diff line
@@ -1015,7 +1015,10 @@ static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu) 
	return probe.present ? 0 : -ENODEV;

}



static int armv8_pmu_init(struct arm_pmu *cpu_pmu)

static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,

			  int (*map_event)(struct perf_event *event),

			  const struct attribute_group *events,

			  const struct attribute_group *format)

{

	int ret = armv8pmu_probe_pmu(cpu_pmu);

	if (ret)
@@ -1034,144 +1037,127 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu) 
	cpu_pmu->set_event_filter	= armv8pmu_set_event_filter;

	cpu_pmu->filter_match		= armv8pmu_filter_match;



	cpu_pmu->name			= name;

	cpu_pmu->map_event		= map_event;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ?

			events : &armv8_pmuv3_events_attr_group;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?

			format : &armv8_pmuv3_format_attr_group;



	return 0;

}



static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)

{

	int ret = armv8_pmu_init(cpu_pmu);

	if (ret)

		return ret;



	cpu_pmu->name			= "armv8_pmuv3";

	cpu_pmu->map_event		= armv8_pmuv3_map_event;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =

		&armv8_pmuv3_events_attr_group;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =

		&armv8_pmuv3_format_attr_group;

	return armv8_pmu_init(cpu_pmu, "armv8_pmuv3",

			      armv8_pmuv3_map_event, NULL, NULL);

}



	return 0;

static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu)

{

	return armv8_pmu_init(cpu_pmu, "armv8_cortex_a34",

			      armv8_pmuv3_map_event, NULL, NULL);

}



static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)

{

	int ret = armv8_pmu_init(cpu_pmu);

	if (ret)

		return ret;



	cpu_pmu->name			= "armv8_cortex_a35";

	cpu_pmu->map_event		= armv8_a53_map_event;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =

		&armv8_pmuv3_events_attr_group;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =

		&armv8_pmuv3_format_attr_group;



	return 0;

	return armv8_pmu_init(cpu_pmu, "armv8_cortex_a35",

			      armv8_a53_map_event, NULL, NULL);

}



static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)

{

	int ret = armv8_pmu_init(cpu_pmu);

	if (ret)

		return ret;



	cpu_pmu->name			= "armv8_cortex_a53";

	cpu_pmu->map_event		= armv8_a53_map_event;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =

		&armv8_pmuv3_events_attr_group;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =

		&armv8_pmuv3_format_attr_group;

	return armv8_pmu_init(cpu_pmu, "armv8_cortex_a53",

			      armv8_a53_map_event, NULL, NULL);

}



	return 0;

static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu)

{

	return armv8_pmu_init(cpu_pmu, "armv8_cortex_a55",

			      armv8_pmuv3_map_event, NULL, NULL);

}



static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)

{

	int ret = armv8_pmu_init(cpu_pmu);

	if (ret)

		return ret;



	cpu_pmu->name			= "armv8_cortex_a57";

	cpu_pmu->map_event		= armv8_a57_map_event;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =

		&armv8_pmuv3_events_attr_group;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =

		&armv8_pmuv3_format_attr_group;

	return armv8_pmu_init(cpu_pmu, "armv8_cortex_a57",

			      armv8_a57_map_event, NULL, NULL);

}



	return 0;

static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu)

{

	return armv8_pmu_init(cpu_pmu, "armv8_cortex_a65",

			      armv8_pmuv3_map_event, NULL, NULL);

}



static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)

{

	int ret = armv8_pmu_init(cpu_pmu);

	if (ret)

		return ret;



	cpu_pmu->name			= "armv8_cortex_a72";

	cpu_pmu->map_event		= armv8_a57_map_event;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =

		&armv8_pmuv3_events_attr_group;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =

		&armv8_pmuv3_format_attr_group;



	return 0;

	return armv8_pmu_init(cpu_pmu, "armv8_cortex_a72",

			      armv8_a57_map_event, NULL, NULL);

}



static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)

{

	int ret = armv8_pmu_init(cpu_pmu);

	if (ret)

		return ret;



	cpu_pmu->name			= "armv8_cortex_a73";

	cpu_pmu->map_event		= armv8_a73_map_event;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =

		&armv8_pmuv3_events_attr_group;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =

		&armv8_pmuv3_format_attr_group;

	return armv8_pmu_init(cpu_pmu, "armv8_cortex_a73",

			      armv8_a73_map_event, NULL, NULL);

}



	return 0;

static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)

{

	return armv8_pmu_init(cpu_pmu, "armv8_cortex_a75",

			      armv8_pmuv3_map_event, NULL, NULL);

}



static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)

static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)

{

	int ret = armv8_pmu_init(cpu_pmu);

	if (ret)

		return ret;

	return armv8_pmu_init(cpu_pmu, "armv8_cortex_a76",

			      armv8_pmuv3_map_event, NULL, NULL);

}



	cpu_pmu->name			= "armv8_cavium_thunder";

	cpu_pmu->map_event		= armv8_thunder_map_event;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =

		&armv8_pmuv3_events_attr_group;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =

		&armv8_pmuv3_format_attr_group;

static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu)

{

	return armv8_pmu_init(cpu_pmu, "armv8_cortex_a77",

			      armv8_pmuv3_map_event, NULL, NULL);

}



	return 0;

static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)

{

	return armv8_pmu_init(cpu_pmu, "armv8_neoverse_e1",

			      armv8_pmuv3_map_event, NULL, NULL);

}



static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)

static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)

{

	int ret = armv8_pmu_init(cpu_pmu);

	if (ret)

		return ret;

	return armv8_pmu_init(cpu_pmu, "armv8_neoverse_n1",

			      armv8_pmuv3_map_event, NULL, NULL);

}



	cpu_pmu->name			= "armv8_brcm_vulcan";

	cpu_pmu->map_event		= armv8_vulcan_map_event;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =

		&armv8_pmuv3_events_attr_group;

	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =

		&armv8_pmuv3_format_attr_group;

static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)

{

	return armv8_pmu_init(cpu_pmu, "armv8_cavium_thunder",

			      armv8_thunder_map_event, NULL, NULL);

}



	return 0;

static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)

{

	return armv8_pmu_init(cpu_pmu, "armv8_brcm_vulcan",

			      armv8_vulcan_map_event, NULL, NULL);

}



static const struct of_device_id armv8_pmu_of_device_ids[] = {

	{.compatible = "arm,armv8-pmuv3",	.data = armv8_pmuv3_init},

	{.compatible = "arm,cortex-a34-pmu",	.data = armv8_a34_pmu_init},

	{.compatible = "arm,cortex-a35-pmu",	.data = armv8_a35_pmu_init},

	{.compatible = "arm,cortex-a53-pmu",	.data = armv8_a53_pmu_init},

	{.compatible = "arm,cortex-a55-pmu",	.data = armv8_a55_pmu_init},

	{.compatible = "arm,cortex-a57-pmu",	.data = armv8_a57_pmu_init},

	{.compatible = "arm,cortex-a65-pmu",	.data = armv8_a65_pmu_init},

	{.compatible = "arm,cortex-a72-pmu",	.data = armv8_a72_pmu_init},

	{.compatible = "arm,cortex-a73-pmu",	.data = armv8_a73_pmu_init},

	{.compatible = "arm,cortex-a75-pmu",	.data = armv8_a75_pmu_init},

	{.compatible = "arm,cortex-a76-pmu",	.data = armv8_a76_pmu_init},

	{.compatible = "arm,cortex-a77-pmu",	.data = armv8_a77_pmu_init},

	{.compatible = "arm,neoverse-e1-pmu",	.data = armv8_e1_pmu_init},

	{.compatible = "arm,neoverse-n1-pmu",	.data = armv8_n1_pmu_init},

	{.compatible = "cavium,thunder-pmu",	.data = armv8_thunder_pmu_init},

	{.compatible = "brcm,vulcan-pmu",	.data = armv8_vulcan_pmu_init},

	{},