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Commit c651aae5 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Catalin Marinas
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arm64: v8.3: Support for weaker release consistency 



ARMv8.3 adds new instructions to support Release Consistent
processor consistent (RCpc) model, which is weaker than the
RCsc model.

Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent cb567e79

Documentation/arm64/cpu-feature-registers.txt

+2 −0
Original line number Diff line number Diff line
@@ -174,6 +174,8 @@ infrastructure: 
     x--------------------------------------------------x

     | Name                         |  bits   | visible |

     |--------------------------------------------------|

     | LRCPC                        | [23-20] |    y    |

     |--------------------------------------------------|

     | FCMA                         | [19-16] |    y    |

     |--------------------------------------------------|

     | JSCVT                        | [15-12] |    y    |

arch/arm64/include/asm/sysreg.h

+1 −0
Original line number Diff line number Diff line
@@ -157,6 +157,7 @@ 
#define ID_AA64ISAR0_AES_SHIFT		4



/* id_aa64isar1 */

#define ID_AA64ISAR1_LRCPC_SHIFT	20

#define ID_AA64ISAR1_FCMA_SHIFT		16

#define ID_AA64ISAR1_JSCVT_SHIFT	12

arch/arm64/include/uapi/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -34,5 +34,6 @@ 
#define HWCAP_ASIMDRDM		(1 << 12)

#define HWCAP_JSCVT		(1 << 13)

#define HWCAP_FCMA		(1 << 14)

#define HWCAP_LRCPC		(1 << 15)



#endif /* _UAPI__ASM_HWCAP_H */

arch/arm64/kernel/cpufeature.c

+2 −0
Original line number Diff line number Diff line
@@ -98,6 +98,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 
};



static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),

	ARM64_FTR_END,
@@ -896,6 +897,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),

	{},

};

arch/arm64/kernel/cpuinfo.c

+1 −0
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ static const char *const hwcap_str[] = { 
	"asimdrdm",

	"jscvt",

	"fcma",

	"lrcpc",

	NULL

};