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Commit c6461f5c authored by Paul Walmsley's avatar Paul Walmsley
Browse files

OMAP2+: clock: disable autoidle on all clocks during clock init 



Disable autoidle on all clocks during clock framework initialization.
(If CONFIG_PM is set, autoidle is re-enabled for all clocks later in
the boot process.)

The principle behind this patch, and some similar patches, is that the
kernel should start with all power management features disabled.
Later in the boot process, the PM code, if compiled in with CONFIG_PM,
enables or re-enables power management features.

Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Tested-by: default avatarRajendra Nayak <rnayak@ti.com>
Reviewed-by: default avatarKevin Hilman <khilman@ti.com>
parent 70db8a62

arch/arm/mach-omap2/clock2420_data.c

+3 −0
Original line number Diff line number Diff line
@@ -1913,6 +1913,9 @@ int __init omap2420_clk_init(void) 
		omap2_init_clk_clkdm(c->lk.clk);

	}



	/* Disable autoidle on all clocks; let the PM code enable it later */

	omap_clk_disable_autoidle_all();



	/* Check the MPU rate set by bootloader */

	clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);

	for (prcm = rate_table; prcm->mpu_speed; prcm++) {

arch/arm/mach-omap2/clock2430_data.c

+3 −0
Original line number Diff line number Diff line
@@ -2028,6 +2028,9 @@ int __init omap2430_clk_init(void) 
		omap2_init_clk_clkdm(c->lk.clk);

	}



	/* Disable autoidle on all clocks; let the PM code enable it later */

	omap_clk_disable_autoidle_all();



	/* Check the MPU rate set by bootloader */

	clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);

	for (prcm = rate_table; prcm->mpu_speed; prcm++) {

arch/arm/mach-omap2/clock3xxx.c

+0 −3
Original line number Diff line number Diff line
@@ -65,9 +65,6 @@ void __init omap3_clk_lock_dpll5(void) 
	clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);

	clk_enable(dpll5_clk);



	/* Enable autoidle to allow it to enter low power bypass */

	omap3_dpll_allow_idle(dpll5_clk);



	/* Program dpll5_m2_clk divider for no division */

	dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");

	clk_enable(dpll5_m2_clk);

arch/arm/mach-omap2/clock3xxx_data.c

+5 −1
Original line number Diff line number Diff line
@@ -3538,6 +3538,9 @@ int __init omap3xxx_clk_init(void) 
			omap2_init_clk_clkdm(c->lk.clk);

		}



	/* Disable autoidle on all clocks; let the PM code enable it later */

	omap_clk_disable_autoidle_all();



	recalculate_root_clocks();



	pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
@@ -3551,7 +3554,8 @@ int __init omap3xxx_clk_init(void) 
	clk_enable_init_clocks();



	/*

	 * Lock DPLL5 and put it in autoidle.

	 * Lock DPLL5 -- here only until other device init code can

	 * handle this

	 */

	if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))

		omap3_clk_lock_dpll5();

arch/arm/mach-omap2/clock44xx_data.c

+3 −0
Original line number Diff line number Diff line
@@ -3309,6 +3309,9 @@ int __init omap4xxx_clk_init(void) 
			omap2_init_clk_clkdm(c->lk.clk);

		}



	/* Disable autoidle on all clocks; let the PM code enable it later */

	omap_clk_disable_autoidle_all();



	recalculate_root_clocks();



	/*