Loading drivers/pci/controller/pci-msm.c +41 −0 Original line number Diff line number Diff line Loading @@ -83,6 +83,11 @@ #define PCIE20_LINK_DOWN_AXI_ECAM_BLOCK_STATUS (0x630) #define PCIE20_PARF_STATUS (0x230) #define PCIE20_PARF_DEBUG_CNT_IN_L0S (0xc10) #define PCIE20_PARF_DEBUG_CNT_IN_L1 (0xc0c) #define PCIE20_PARF_DEBUG_CNT_IN_L1SUB_L1 (0xc84) #define PCIE20_PARF_DEBUG_CNT_IN_L1SUB_L2 (0xc88) #define PCIE20_PARF_CLKREQ_OVERRIDE (0x2b0) #define PCIE20_PARF_CLKREQ_IN_VALUE (BIT(3)) #define PCIE20_PARF_CLKREQ_IN_ENABLE (BIT(1)) Loading Loading @@ -332,6 +337,7 @@ enum msm_pcie_res { MSM_PCIE_RES_ELBI, MSM_PCIE_RES_IATU, MSM_PCIE_RES_CONF, MSM_PCIE_RES_MHI, MSM_PCIE_RES_TCSR, MSM_PCIE_RES_RUMI, MSM_PCIE_MAX_RES, Loading Loading @@ -710,6 +716,7 @@ struct msm_pcie_dev_t { void __iomem *iatu; void __iomem *dm_core; void __iomem *conf; void __iomem *mhi; void __iomem *tcsr; void __iomem *rumi; Loading Loading @@ -1063,6 +1070,7 @@ static const struct msm_pcie_res_info_t msm_pcie_res_info[MSM_PCIE_MAX_RES] = { {"elbi", NULL, NULL}, {"iatu", NULL, NULL}, {"conf", NULL, NULL}, {"mhi", NULL, NULL}, {"tcsr", NULL, NULL}, {"rumi", NULL, NULL} }; Loading Loading @@ -2133,6 +2141,36 @@ static ssize_t enumerate_store(struct device *dev, } static DEVICE_ATTR_WO(enumerate); static ssize_t aspm_stat_show(struct device *dev, struct device_attribute *attr, char *buf) { struct msm_pcie_dev_t *pcie_dev = dev_get_drvdata(dev); if (!pcie_dev->mhi) return scnprintf(buf, PAGE_SIZE, "PCIe: RC%d: No dev or MHI space found\n", pcie_dev->rc_idx); if (pcie_dev->link_status != MSM_PCIE_LINK_ENABLED) return scnprintf(buf, PAGE_SIZE, "PCIe: RC%d: registers are not accessible\n", pcie_dev->rc_idx); return scnprintf(buf, PAGE_SIZE, "PCIe: RC%d: L0s: %u L1: %u L1.1: %u L1.2: %u\n", pcie_dev->rc_idx, readl_relaxed(pcie_dev->mhi + PCIE20_PARF_DEBUG_CNT_IN_L0S), readl_relaxed(pcie_dev->mhi + PCIE20_PARF_DEBUG_CNT_IN_L1), readl_relaxed(pcie_dev->mhi + PCIE20_PARF_DEBUG_CNT_IN_L1SUB_L1), readl_relaxed(pcie_dev->mhi + PCIE20_PARF_DEBUG_CNT_IN_L1SUB_L2)); } static DEVICE_ATTR_RO(aspm_stat); static ssize_t l23_rdy_poll_timeout_show(struct device *dev, struct device_attribute *attr, char *buf) Loading Loading @@ -2167,6 +2205,7 @@ static DEVICE_ATTR_RW(l23_rdy_poll_timeout); static struct attribute *msm_pcie_debug_attrs[] = { &dev_attr_link_check_max_count.attr, &dev_attr_enumerate.attr, &dev_attr_aspm_stat.attr, &dev_attr_l23_rdy_poll_timeout.attr, NULL, }; Loading Loading @@ -4066,6 +4105,7 @@ static int msm_pcie_get_reg(struct msm_pcie_dev_t *pcie_dev) pcie_dev->iatu = pcie_dev->res[MSM_PCIE_RES_IATU].base; pcie_dev->dm_core = pcie_dev->res[MSM_PCIE_RES_DM_CORE].base; pcie_dev->conf = pcie_dev->res[MSM_PCIE_RES_CONF].base; pcie_dev->mhi = pcie_dev->res[MSM_PCIE_RES_MHI].base; pcie_dev->tcsr = pcie_dev->res[MSM_PCIE_RES_TCSR].base; pcie_dev->rumi = pcie_dev->res[MSM_PCIE_RES_RUMI].base; Loading Loading @@ -4182,6 +4222,7 @@ static void msm_pcie_release_resources(struct msm_pcie_dev_t *dev) dev->iatu = NULL; dev->dm_core = NULL; dev->conf = NULL; dev->mhi = NULL; dev->tcsr = NULL; dev->rumi = NULL; } Loading Loading
drivers/pci/controller/pci-msm.c +41 −0 Original line number Diff line number Diff line Loading @@ -83,6 +83,11 @@ #define PCIE20_LINK_DOWN_AXI_ECAM_BLOCK_STATUS (0x630) #define PCIE20_PARF_STATUS (0x230) #define PCIE20_PARF_DEBUG_CNT_IN_L0S (0xc10) #define PCIE20_PARF_DEBUG_CNT_IN_L1 (0xc0c) #define PCIE20_PARF_DEBUG_CNT_IN_L1SUB_L1 (0xc84) #define PCIE20_PARF_DEBUG_CNT_IN_L1SUB_L2 (0xc88) #define PCIE20_PARF_CLKREQ_OVERRIDE (0x2b0) #define PCIE20_PARF_CLKREQ_IN_VALUE (BIT(3)) #define PCIE20_PARF_CLKREQ_IN_ENABLE (BIT(1)) Loading Loading @@ -332,6 +337,7 @@ enum msm_pcie_res { MSM_PCIE_RES_ELBI, MSM_PCIE_RES_IATU, MSM_PCIE_RES_CONF, MSM_PCIE_RES_MHI, MSM_PCIE_RES_TCSR, MSM_PCIE_RES_RUMI, MSM_PCIE_MAX_RES, Loading Loading @@ -710,6 +716,7 @@ struct msm_pcie_dev_t { void __iomem *iatu; void __iomem *dm_core; void __iomem *conf; void __iomem *mhi; void __iomem *tcsr; void __iomem *rumi; Loading Loading @@ -1063,6 +1070,7 @@ static const struct msm_pcie_res_info_t msm_pcie_res_info[MSM_PCIE_MAX_RES] = { {"elbi", NULL, NULL}, {"iatu", NULL, NULL}, {"conf", NULL, NULL}, {"mhi", NULL, NULL}, {"tcsr", NULL, NULL}, {"rumi", NULL, NULL} }; Loading Loading @@ -2133,6 +2141,36 @@ static ssize_t enumerate_store(struct device *dev, } static DEVICE_ATTR_WO(enumerate); static ssize_t aspm_stat_show(struct device *dev, struct device_attribute *attr, char *buf) { struct msm_pcie_dev_t *pcie_dev = dev_get_drvdata(dev); if (!pcie_dev->mhi) return scnprintf(buf, PAGE_SIZE, "PCIe: RC%d: No dev or MHI space found\n", pcie_dev->rc_idx); if (pcie_dev->link_status != MSM_PCIE_LINK_ENABLED) return scnprintf(buf, PAGE_SIZE, "PCIe: RC%d: registers are not accessible\n", pcie_dev->rc_idx); return scnprintf(buf, PAGE_SIZE, "PCIe: RC%d: L0s: %u L1: %u L1.1: %u L1.2: %u\n", pcie_dev->rc_idx, readl_relaxed(pcie_dev->mhi + PCIE20_PARF_DEBUG_CNT_IN_L0S), readl_relaxed(pcie_dev->mhi + PCIE20_PARF_DEBUG_CNT_IN_L1), readl_relaxed(pcie_dev->mhi + PCIE20_PARF_DEBUG_CNT_IN_L1SUB_L1), readl_relaxed(pcie_dev->mhi + PCIE20_PARF_DEBUG_CNT_IN_L1SUB_L2)); } static DEVICE_ATTR_RO(aspm_stat); static ssize_t l23_rdy_poll_timeout_show(struct device *dev, struct device_attribute *attr, char *buf) Loading Loading @@ -2167,6 +2205,7 @@ static DEVICE_ATTR_RW(l23_rdy_poll_timeout); static struct attribute *msm_pcie_debug_attrs[] = { &dev_attr_link_check_max_count.attr, &dev_attr_enumerate.attr, &dev_attr_aspm_stat.attr, &dev_attr_l23_rdy_poll_timeout.attr, NULL, }; Loading Loading @@ -4066,6 +4105,7 @@ static int msm_pcie_get_reg(struct msm_pcie_dev_t *pcie_dev) pcie_dev->iatu = pcie_dev->res[MSM_PCIE_RES_IATU].base; pcie_dev->dm_core = pcie_dev->res[MSM_PCIE_RES_DM_CORE].base; pcie_dev->conf = pcie_dev->res[MSM_PCIE_RES_CONF].base; pcie_dev->mhi = pcie_dev->res[MSM_PCIE_RES_MHI].base; pcie_dev->tcsr = pcie_dev->res[MSM_PCIE_RES_TCSR].base; pcie_dev->rumi = pcie_dev->res[MSM_PCIE_RES_RUMI].base; Loading Loading @@ -4182,6 +4222,7 @@ static void msm_pcie_release_resources(struct msm_pcie_dev_t *dev) dev->iatu = NULL; dev->dm_core = NULL; dev->conf = NULL; dev->mhi = NULL; dev->tcsr = NULL; dev->rumi = NULL; } Loading