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Commit c589225b authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Avoid slumber if interrupt is pending"

parents 775a0853 f8d51faf

drivers/gpu/msm/adreno.c

+7 −2
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2002,2007-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2002,2007-2021, The Linux Foundation. All rights reserved.

 */

#include <linux/component.h>

#include <linux/delay.h>
@@ -2612,7 +2612,12 @@ static int adreno_setproperty(struct kgsl_device_private *dev_priv, 
bool adreno_irq_pending(struct adreno_device *adreno_dev)

{

	unsigned int status;

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);



	if (gmu_core_isenabled(device))

		adreno_read_gmureg(adreno_dev,

			ADRENO_REG_GMU_AO_RBBM_INT_UNMASKED_STATUS, &status);

	else

		adreno_readreg(adreno_dev, ADRENO_REG_RBBM_INT_0_STATUS, &status);



	/*

drivers/gpu/msm/adreno.h

+2 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2008-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2008-2021, The Linux Foundation. All rights reserved.

 */

#ifndef __ADRENO_H

#define __ADRENO_H
@@ -702,6 +702,7 @@ enum adreno_regs { 
	ADRENO_REG_GMU_AHB_FENCE_STATUS,

	ADRENO_REG_GMU_GMU2HOST_INTR_MASK,

	ADRENO_REG_GPMU_POWER_COUNTER_ENABLE,

	ADRENO_REG_GMU_AO_RBBM_INT_UNMASKED_STATUS,

	ADRENO_REG_REGISTER_MAX,

};

drivers/gpu/msm/adreno_a6xx.c

+3 −2
Original line number Diff line number Diff line
@@ -1250,9 +1250,8 @@ bool a6xx_hw_isidle(struct adreno_device *adreno_dev) 
	}



	gmu_core_regread(device, A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, &reg);



	/* Bit 23 is GPUBUSYIGNAHB */

	return (reg & BIT(23)) ? false : true;

	return ((reg & BIT(23)) || adreno_irq_pending(adreno_dev)) ? false : true;

}



int a6xx_microcode_read(struct adreno_device *adreno_dev)
@@ -2398,6 +2397,8 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
				A6XX_GMU_AHB_FENCE_STATUS),

	ADRENO_REG_DEFINE(ADRENO_REG_GMU_GMU2HOST_INTR_MASK,

				A6XX_GMU_GMU2HOST_INTR_MASK),

	ADRENO_REG_DEFINE(ADRENO_REG_GMU_AO_RBBM_INT_UNMASKED_STATUS,

				A6XX_GMU_RBBM_INT_UNMASKED_STATUS),

};



static int cpu_gpu_lock(struct cpu_gpu_lock *lock)