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Commit c54fdbb2 authored by Feng Tang's avatar Feng Tang Committed by John Stultz
Browse files

x86: Add cpu capability flag X86_FEATURE_NONSTOP_TSC_S3 



On some new Intel Atom processors (Penwell and Cloverview), there is
a feature that the TSC won't stop in S3 state, say the TSC value
won't be reset to 0 after resume. This feature makes TSC a more reliable
clocksource and could benefit the timekeeping code during system
suspend/resume cycle, so add a flag for it.

Signed-off-by: default avatarFeng Tang <feng.tang@intel.com>
[jstultz: Fix checkpatch warning]
Signed-off-by: default avatarJohn Stultz <john.stultz@linaro.org>
parent 3195ef59

arch/x86/include/asm/cpufeature.h

+1 −0
Original line number Diff line number Diff line
@@ -100,6 +100,7 @@ 
#define X86_FEATURE_AMD_DCM     (3*32+27) /* multi-node processor */

#define X86_FEATURE_APERFMPERF	(3*32+28) /* APERFMPERF */

#define X86_FEATURE_EAGER_FPU	(3*32+29) /* "eagerfpu" Non lazy FPU restore */

#define X86_FEATURE_NONSTOP_TSC_S3 (3*32+30) /* TSC doesn't stop in S3 state */



/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */

#define X86_FEATURE_XMM3	(4*32+ 0) /* "pni" SSE-3 */

arch/x86/kernel/cpu/intel.c

+12 −0
Original line number Diff line number Diff line
@@ -96,6 +96,18 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) 
			sched_clock_stable = 1;

	}



	/* Penwell and Cloverview have the TSC which doesn't sleep on S3 */

	if (c->x86 == 6) {

		switch (c->x86_model) {

		case 0x27:	/* Penwell */

		case 0x35:	/* Cloverview */

			set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);

			break;

		default:

			break;

		}

	}



	/*

	 * There is a known erratum on Pentium III and Core Solo

	 * and Core Duo CPUs.