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Commit c534c6d2 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "cnss2: Refactor registers dump APIs"

parents 38b09e63 241ff88b

drivers/net/wireless/cnss2/pci.c

+305 −253

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/wireless/cnss2/pci.h

+9 −3
Original line number Diff line number Diff line
@@ -39,6 +39,12 @@ enum cnss_rtpm_id { 
	RTPM_ID_MAX,

};



enum cnss_pci_reg_dev_mask {

	REG_MASK_QCA6390,

	REG_MASK_QCA6490,

	REG_MASK_WCN7850,

};



struct cnss_msi_user {

	char *name;

	int num_vectors;
@@ -62,6 +68,7 @@ struct cnss_pci_debug_reg { 
};



struct cnss_misc_reg {

	unsigned long dev_mask;

	u8 wr;

	u32 offset;

	u32 val;
@@ -122,11 +129,10 @@ struct cnss_pci_data { 
	struct mutex bus_lock; /* mutex for suspend and resume bus */

	struct cnss_pci_debug_reg *debug_reg;

	struct cnss_misc_reg *wcss_reg;

	u32 wcss_reg_size;

	struct cnss_misc_reg *pcie_reg;

	u32 pcie_reg_size;

	struct cnss_misc_reg *wlaon_reg;

	u32 wlaon_reg_size;

	struct cnss_misc_reg *syspm_reg;

	unsigned long misc_reg_dev_mask;

	u8 iommu_geometry;

	bool drv_supported;

};

drivers/net/wireless/cnss2/reg.h

+132 −98
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */

/* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */



#ifndef _CNSS_REG_H

#define _CNSS_REG_H
@@ -48,9 +48,6 @@ 
#define QCA6390_PCIE_SHADOW_REG_VALUE_0		0x8FC

#define QCA6390_PCIE_SHADOW_REG_VALUE_34	0x984

#define QCA6390_PCIE_SHADOW_REG_VALUE_35	0x988

#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL3	0x1F80118

#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL4	0x1F8011C

#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL5	0x1F80120



#define SHADOW_REG_INTER_COUNT			43

#define QCA6390_PCIE_SHADOW_REG_INTER_0		0x1E05000
@@ -165,102 +162,139 @@ 
#define QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN2_APS_STATUS_REG1 0x00B600B0

#define QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1 0x00B60044



#define QCA6390_WLAON_WCSSAON_PCIE_SR_STATUS_HI_REG 0x01F806C4

#define QCA6390_WLAON_SOC_POWER_CTRL 0x01F80000

#define QCA6390_WLAON_PCIE_PWR_CTRL_REG 0x01F806BC

#define QCA6390_WLAON_WCSSAON_PCIE_SR_STATUS_LO_REG 0x1F806C8

#define QCA6390_WLAON_WCSS_TCSR_PMM_SR_STATUS_HI_REG 0x1F806CC

#define QCA6390_WLAON_WCSS_TCSR_PMM_SR_STATUS_LO_REG 0x1F806D0

#define QCA6390_WLAON_SOC_PWR_WDG_BARK_THRSHD 0x1F80004

#define QCA6390_WLAON_SOC_PWR_WDG_BITE_THRSHD 0x1F80008

#define QCA6390_WLAON_SW_COLD_RESET 0x1F8000C

#define QCA6390_WLAON_RFA_MEM_SLP_NRET_N_OVERRIDE 0x1F8001C

#define QCA6390_WLAON_GDSC_DELAY_SETTING 0x1F80024

#define QCA6390_WLAON_GDSC_DELAY_SETTING2 0x1F80028

#define QCA6390_WLAON_WL_PWR_STATUS_REG 0x1F8002C

#define QCA6390_WLAON_WL_AON_DBG_CFG_REG 0x1F80030

#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL1 0x1F80100

#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL6 0x1F80108

#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL7 0x1F8010C

#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL3 0x1F80118

#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL4 0x1F8011C

#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL5 0x1F80120

#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL8 0x1F801F0

#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL2 0x1F801F4

#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL9 0x1F801F8

#define QCA6390_WLAON_RTC_CLK_CAL_CTRL1 0x1F80200

#define QCA6390_WLAON_RTC_CLK_CAL_CTRL2 0x1F80204

#define QCA6390_WLAON_RTC_CLK_CAL_CTRL3 0x1F80208

#define QCA6390_WLAON_RTC_CLK_CAL_CTRL4 0x1F8020C

#define QCA6390_WLAON_RTC_CLK_CAL_CTRL5 0x1F80210

#define QCA6390_WLAON_RTC_CLK_CAL_CTRL6 0x1F80214

#define QCA6390_WLAON_RTC_CLK_CAL_CTRL7 0x1F80218

#define QCA6390_WLAON_RTC_CLK_CAL_CTRL8 0x1F8021C

#define QCA6390_WLAON_RTC_CLK_CAL_CTRL9 0x1F80220

#define QCA6390_WLAON_WCSSAON_CONFIG_REG 0x1F80300

#define QCA6390_WLAON_WLAN_OEM_DEBUG_REG 0x1F80304

#define QCA6390_WLAON_WLAN_RAM_DUMP_REG 0x1F80308

#define QCA6390_WLAON_QDSS_WCSS_REG 0x1F8030C

#define QCA6390_WLAON_QDSS_WCSS_ACK 0x1F80310

#define QCA6390_WLAON_WL_CLK_CNTL_KDF_REG 0x1F80314

#define QCA6390_WLAON_WL_CLK_CNTL_PMU_HFRC_REG 0x1F80318

#define QCA6390_WLAON_QFPROM_PWR_CTRL_REG 0x1F8031C

#define WLAON_SOC_POWER_CTRL 0x01F80000

#define WLAON_SOC_PWR_WDG_BARK_THRSHD 0x1F80004

#define WLAON_SOC_PWR_WDG_BITE_THRSHD 0x1F80008

#define WLAON_SW_COLD_RESET 0x1F8000C

#define WLAON_RFA_MEM_SLP_NRET_N_OVERRIDE 0x1F8001C

#define WLAON_GDSC_DELAY_SETTING 0x1F80024

#define WLAON_GDSC_DELAY_SETTING2 0x1F80028

#define WLAON_WL_PWR_STATUS_REG 0x1F8002C

#define WLAON_WL_AON_DBG_CFG_REG 0x1F80030

#define WLAON_WL_AON_DBG_ENABLE_GRP0_REG 0x1F80034

#define WLAON_WL_AON_DBG_ENABLE_GRP1_REG 0x1F80038

#define WLAON_WL_AON_APM_CFG_CTRL0 0x1F80040

#define WLAON_WL_AON_APM_CFG_CTRL1 0x1F80044

#define WLAON_WL_AON_APM_CFG_CTRL2 0x1F80048

#define WLAON_WL_AON_APM_CFG_CTRL3 0x1F8004C

#define WLAON_WL_AON_APM_CFG_CTRL4 0x1F80050

#define WLAON_WL_AON_APM_CFG_CTRL5 0x1F80054

#define WLAON_WL_AON_APM_CFG_CTRL5_1 0x1F80058

#define WLAON_WL_AON_APM_CFG_CTRL6 0x1F8005C

#define WLAON_WL_AON_APM_CFG_CTRL6_1 0x1F80060

#define WLAON_WL_AON_APM_CFG_CTRL7 0x1F80064

#define WLAON_WL_AON_APM_CFG_CTRL8 0x1F80068

#define WLAON_WL_AON_APM_CFG_CTRL8_1 0x1F8006C

#define WLAON_WL_AON_APM_CFG_CTRL9 0x1F80070

#define WLAON_WL_AON_APM_CFG_CTRL9_1 0x1F80074

#define WLAON_WL_AON_APM_CFG_CTRL10 0x1F80078

#define WLAON_WL_AON_APM_CFG_CTRL11 0x1F8007C

#define WLAON_WL_AON_APM_CFG_CTRL12 0x1F80080

#define WLAON_WL_AON_APM_OVERRIDE_REG 0x1F800B0

#define WLAON_WL_AON_CXPC_REG 0x1F800B4

#define WLAON_WL_AON_APM_STATUS0 0x1F800C0

#define WLAON_WL_AON_APM_STATUS1 0x1F800C4

#define WLAON_WL_AON_APM_STATUS2 0x1F800C8

#define WLAON_WL_AON_APM_STATUS3 0x1F800CC

#define WLAON_WL_AON_APM_STATUS4 0x1F800D0

#define WLAON_WL_AON_APM_STATUS5 0x1F800D4

#define WLAON_WL_AON_APM_STATUS6 0x1F800D8

#define WLAON_GLOBAL_COUNTER_CTRL1 0x1F80100

#define WLAON_GLOBAL_COUNTER_CTRL6 0x1F80108

#define WLAON_GLOBAL_COUNTER_CTRL7 0x1F8010C

#define WLAON_GLOBAL_COUNTER_CTRL3 0x1F80118

#define WLAON_GLOBAL_COUNTER_CTRL4 0x1F8011C

#define WLAON_GLOBAL_COUNTER_CTRL5 0x1F80120

#define WLAON_GLOBAL_COUNTER_CTRL8 0x1F801F0

#define WLAON_GLOBAL_COUNTER_CTRL2 0x1F801F4

#define WLAON_GLOBAL_COUNTER_CTRL9 0x1F801F8

#define WLAON_RTC_CLK_CAL_CTRL1 0x1F80200

#define WLAON_RTC_CLK_CAL_CTRL2 0x1F80204

#define WLAON_RTC_CLK_CAL_CTRL3 0x1F80208

#define WLAON_RTC_CLK_CAL_CTRL4 0x1F8020C

#define WLAON_RTC_CLK_CAL_CTRL5 0x1F80210

#define WLAON_RTC_CLK_CAL_CTRL6 0x1F80214

#define WLAON_RTC_CLK_CAL_CTRL7 0x1F80218

#define WLAON_RTC_CLK_CAL_CTRL8 0x1F8021C

#define WLAON_RTC_CLK_CAL_CTRL9 0x1F80220

#define WLAON_WCSSAON_CONFIG_REG 0x1F80300

#define WLAON_WLAN_OEM_DEBUG_REG 0x1F80304

#define WLAON_WLAN_RAM_DUMP_REG 0x1F80308

#define WLAON_QDSS_WCSS_REG 0x1F8030C

#define WLAON_QDSS_WCSS_ACK 0x1F80310

#define WLAON_WL_CLK_CNTL_KDF_REG 0x1F80314

#define WLAON_WL_CLK_CNTL_PMU_HFRC_REG 0x1F80318

#define WLAON_QFPROM_PWR_CTRL_REG 0x1F8031C

#define QFPROM_PWR_CTRL_VDD4BLOW_SW_EN_MASK 0x4

#define QFPROM_PWR_CTRL_SHUTDOWN_EN_MASK 0x1

#define QCA6390_WLAON_DLY_CONFIG 0x1F80400

#define QCA6390_WLAON_WLAON_Q6_IRQ_REG 0x1F80404

#define QCA6390_WLAON_PCIE_INTF_SW_CFG_REG 0x1F80408

#define QCA6390_WLAON_PCIE_INTF_STICKY_SW_CFG_REG 0x1F8040C

#define QCA6390_WLAON_PCIE_INTF_PHY_SW_CFG_REG 0x1F80410

#define QCA6390_WLAON_PCIE_INTF_PHY_NOCSR_SW_CFG_REG 0x1F80414

#define QCA6390_WLAON_Q6_COOKIE_BIT 0x1F80500

#define QCA6390_WLAON_WARM_SW_ENTRY 0x1F80504

#define QCA6390_WLAON_RESET_DBG_SW_ENTRY 0x1F80508

#define QCA6390_WLAON_WL_PMUNOC_CFG_REG 0x1F8050C

#define QCA6390_WLAON_RESET_CAUSE_CFG_REG 0x1F80510

#define QCA6390_WLAON_SOC_WCSSAON_WAKEUP_IRQ_7_EN_REG 0x1F80514

#define QCA6390_WLAON_DEBUG 0x1F80600

#define QCA6390_WLAON_SOC_PARAMETERS 0x1F80604

#define QCA6390_WLAON_WLPM_SIGNAL 0x1F80608

#define QCA6390_WLAON_SOC_RESET_CAUSE_REG 0x1F8060C

#define QCA6390_WLAON_WAKEUP_PCIE_SOC_REG 0x1F80610

#define QCA6390_WLAON_PBL_STACK_CANARY 0x1F80614

#define QCA6390_WLAON_MEM_TOT_NUM_GRP_REG 0x1F80618

#define QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP0_REG 0x1F8061C

#define QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP1_REG 0x1F80620

#define QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP2_REG 0x1F80624

#define QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP3_REG 0x1F80628

#define QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP0_REG 0x1F8062C

#define QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP1_REG 0x1F80630

#define QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP2_REG 0x1F80634

#define QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP3_REG 0x1F80638

#define QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP0_REG 0x1F8063C

#define QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP1_REG 0x1F80640

#define QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP2_REG 0x1F80644

#define QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP3_REG 0x1F80648

#define QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP0_REG 0x1F8064C

#define QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP1_REG 0x1F80650

#define QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP2_REG 0x1F80654

#define QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP3_REG 0x1F80658

#define QCA6390_WLAON_MEM_CNT_SEL_REG 0x1F8065C

#define QCA6390_WLAON_MEM_NO_EXTBHS_REG 0x1F80660

#define QCA6390_WLAON_MEM_DEBUG_REG 0x1F80664

#define QCA6390_WLAON_MEM_DEBUG_BUS_REG 0x1F80668

#define QCA6390_WLAON_MEM_REDUN_CFG_REG 0x1F8066C

#define QCA6390_WLAON_WL_AON_SPARE2 0x1F80670

#define QCA6390_WLAON_VSEL_CFG_FOR_WL_RET_DISABLE_REG 0x1F80680

#define QCA6390_WLAON_BTFM_WLAN_IPC_STATUS_REG 0x1F80690

#define QCA6390_WLAON_MPM_COUNTER_CHICKEN_BITS 0x1F806A0

#define QCA6390_WLAON_WLPM_CHICKEN_BITS 0x1F806A4

#define QCA6390_WLAON_PCIE_PHY_PWR_REG 0x1F806A8

#define QCA6390_WLAON_WL_CLK_CNTL_PMU_LPO2M_REG 0x1F806AC

#define QCA6390_WLAON_WL_SS_ROOT_CLK_SWITCH_REG 0x1F806B0

#define QCA6390_WLAON_POWERCTRL_PMU_REG 0x1F806B4

#define QCA6390_WLAON_POWERCTRL_MEM_REG 0x1F806B8

#define QCA6390_WLAON_SOC_PWR_PROFILE_REG 0x1F806C0

#define QCA6390_WLAON_MEM_SVS_CFG_REG 0x1F806D4

#define QCA6390_WLAON_CMN_AON_MISC_REG 0x1F806D8

#define QCA6390_WLAON_INTR_STATUS 0x1F80700

#define WLAON_DLY_CONFIG 0x1F80400

#define WLAON_WLAON_Q6_IRQ_REG 0x1F80404

#define WLAON_PCIE_INTF_SW_CFG_REG 0x1F80408

#define WLAON_PCIE_INTF_STICKY_SW_CFG_REG 0x1F8040C

#define WLAON_PCIE_INTF_PHY_SW_CFG_REG 0x1F80410

#define WLAON_PCIE_INTF_PHY_NOCSR_SW_CFG_REG 0x1F80414

#define WLAON_Q6_COOKIE_BIT 0x1F80500

#define WLAON_WARM_SW_ENTRY 0x1F80504

#define WLAON_RESET_DBG_SW_ENTRY 0x1F80508

#define WLAON_WL_PMUNOC_CFG_REG 0x1F8050C

#define WLAON_RESET_CAUSE_CFG_REG 0x1F80510

#define WLAON_SOC_WCSSAON_WAKEUP_IRQ_7_EN_REG 0x1F80514

#define WLAON_DEBUG 0x1F80600

#define WLAON_SOC_PARAMETERS 0x1F80604

#define WLAON_WLPM_SIGNAL 0x1F80608

#define WLAON_SOC_RESET_CAUSE_REG 0x1F8060C

#define WLAON_WAKEUP_PCIE_SOC_REG 0x1F80610

#define WLAON_PBL_STACK_CANARY 0x1F80614

#define WLAON_MEM_TOT_NUM_GRP_REG 0x1F80618

#define WLAON_MEM_TOT_BANKS_IN_GRP0_REG 0x1F8061C

#define WLAON_MEM_TOT_BANKS_IN_GRP1_REG 0x1F80620

#define WLAON_MEM_TOT_BANKS_IN_GRP2_REG 0x1F80624

#define WLAON_MEM_TOT_BANKS_IN_GRP3_REG 0x1F80628

#define WLAON_MEM_TOT_SIZE_IN_GRP0_REG 0x1F8062C

#define WLAON_MEM_TOT_SIZE_IN_GRP1_REG 0x1F80630

#define WLAON_MEM_TOT_SIZE_IN_GRP2_REG 0x1F80634

#define WLAON_MEM_TOT_SIZE_IN_GRP3_REG 0x1F80638

#define WLAON_MEM_SLP_NRET_OVERRIDE_GRP0_REG 0x1F8063C

#define WLAON_MEM_SLP_NRET_OVERRIDE_GRP1_REG 0x1F80640

#define WLAON_MEM_SLP_NRET_OVERRIDE_GRP2_REG 0x1F80644

#define WLAON_MEM_SLP_NRET_OVERRIDE_GRP3_REG 0x1F80648

#define WLAON_MEM_SLP_RET_OVERRIDE_GRP0_REG 0x1F8064C

#define WLAON_MEM_SLP_RET_OVERRIDE_GRP1_REG 0x1F80650

#define WLAON_MEM_SLP_RET_OVERRIDE_GRP2_REG 0x1F80654

#define WLAON_MEM_SLP_RET_OVERRIDE_GRP3_REG 0x1F80658

#define WLAON_MEM_CNT_SEL_REG 0x1F8065C

#define WLAON_MEM_NO_EXTBHS_REG 0x1F80660

#define WLAON_MEM_DEBUG_REG 0x1F80664

#define WLAON_MEM_DEBUG_BUS_REG 0x1F80668

#define WLAON_MEM_REDUN_CFG_REG 0x1F8066C

#define WLAON_WL_AON_SPARE2 0x1F80670

#define WLAON_VSEL_CFG_FOR_WL_RET_DISABLE_REG 0x1F80680

#define WLAON_BTFM_WLAN_IPC_STATUS_REG 0x1F80690

#define WLAON_MPM_COUNTER_CHICKEN_BITS 0x1F806A0

#define WLAON_WLPM_CHICKEN_BITS 0x1F806A4

#define WLAON_PCIE_PHY_PWR_REG 0x1F806A8

#define WLAON_WL_CLK_CNTL_PMU_LPO2M_REG 0x1F806AC

#define WLAON_WL_SS_ROOT_CLK_SWITCH_REG 0x1F806B0

#define WLAON_POWERCTRL_PMU_REG 0x1F806B4

#define WLAON_POWERCTRL_MEM_REG 0x1F806B8

#define WLAON_PCIE_PWR_CTRL_REG 0x01F806BC

#define WLAON_SOC_PWR_PROFILE_REG 0x1F806C0

#define WLAON_WCSSAON_PCIE_SR_STATUS_HI_REG 0x01F806C4

#define WLAON_WCSSAON_PCIE_SR_STATUS_LO_REG 0x1F806C8

#define WLAON_WCSS_TCSR_PMM_SR_STATUS_HI_REG 0x1F806CC

#define WLAON_WCSS_TCSR_PMM_SR_STATUS_LO_REG 0x1F806D0

#define WLAON_MEM_SVS_CFG_REG 0x1F806D4

#define WLAON_CMN_AON_MISC_REG 0x1F806D8

#define WLAON_INTR_STATUS 0x1F80700

#define WLAON_INTR_ENABLE 0x1F807040

#define WLAON_NOC_DBG_BUS_SEL_REG 0x1F80708

#define WLAON_NOC_DBG_BUS_REG 0x1F8070C

#define WLAON_WL_CTRL_MISC_REG 0x1F80710

#define WLAON_DBG_STATUS0 0x1F80720

#define WLAON_DBG_STATUS1 0x1F80724

#define WLAON_TIMERSYNC_OFFSET_L 0x1F80730

#define WLAON_TIMERSYNC_OFFSET_H 0x1F80734

#define WLAON_PMU_LDO_SETTLE_REG 0x1F80740



#define QCA6390_SYSPM_SYSPM_PWR_STATUS 0x1F82000

#define QCA6390_SYSPM_DBG_BTFM_AON_REG 0x1F82004