Loading qcom/lahaina.dtsi +2 −1 Original line number Diff line number Diff line Loading @@ -2684,7 +2684,8 @@ clocks = <&clock_gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, <&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, <&clock_gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&clock_rpmh RPMH_IPA_CLK>; }; clk_virt: interconnect { Loading Loading
qcom/lahaina.dtsi +2 −1 Original line number Diff line number Diff line Loading @@ -2684,7 +2684,8 @@ clocks = <&clock_gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, <&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, <&clock_gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&clock_rpmh RPMH_IPA_CLK>; }; clk_virt: interconnect { Loading