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Commit c437f65c authored by David Wu's avatar David Wu Committed by Linus Walleij
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pinctrl: rockchip: Fix the rk3399 gpio0 and gpio1 banks' drv_offset at pmu grf 



The offset of gpio0 and gpio1 bank drive strength is 0x8, not 0x4.
But the mux is 0x4, we couldn't use the IOMUX_WIDTH_4BIT flag, so
we give them actual offset.

Signed-off-by: default avatarDavid Wu <david.wu@rock-chips.com>
Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 2dca9227

drivers/pinctrl/pinctrl-rockchip.c

+6 −6
Original line number Diff line number Diff line
@@ -3456,8 +3456,8 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = { 
							 DRV_TYPE_IO_1V8_ONLY,

							 DRV_TYPE_IO_DEFAULT,

							 DRV_TYPE_IO_DEFAULT,

							 0x0,

							 0x8,

							 0x80,

							 0x88,

							 -1,

							 -1,

							 PULL_TYPE_IO_1V8_ONLY,
@@ -3473,10 +3473,10 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = { 
					DRV_TYPE_IO_1V8_OR_3V0,

					DRV_TYPE_IO_1V8_OR_3V0,

					DRV_TYPE_IO_1V8_OR_3V0,

					0x20,

					0x28,

					0x30,

					0x38

					0xa0,

					0xa8,

					0xb0,

					0xb8

					),

	PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,

				      DRV_TYPE_IO_1V8_OR_3V0,