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Unverified Commit c3e6845e authored by Ludovic Barre's avatar Ludovic Barre Committed by Mark Brown
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dt-bindings: spi: add stm32 qspi controller 



This patch adds the documentation of device tree bindings
for the STM32 QSPI controller. It is a specialized communication
interface targeting single, dual or quad SPI Flash memories (NOR/NAND).

Signed-off-by: default avatarLudovic Barre <ludovic.barre@st.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent a27ee74d

Documentation/devicetree/bindings/spi/spi-stm32-qspi.txt

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* STMicroelectronics Quad Serial Peripheral Interface(QSPI)



Required properties:

- compatible: should be "st,stm32f469-qspi"

- reg: the first contains the register location and length.

       the second contains the memory mapping address and length

- reg-names: should contain the reg names "qspi" "qspi_mm"

- interrupts: should contain the interrupt for the device

- clocks: the phandle of the clock needed by the QSPI controller

- A pinctrl must be defined to set pins in mode of operation for QSPI transfer



Optional properties:

- resets: must contain the phandle to the reset controller.



A spi flash (NOR/NAND) must be a child of spi node and could have some

properties. Also see jedec,spi-nor.txt.



Required properties:

- reg: chip-Select number (QSPI controller may connect 2 flashes)

- spi-max-frequency: max frequency of spi bus



Optional property:

- spi-rx-bus-width: see ./spi-bus.txt for the description



Example:



qspi: spi@a0001000 {

	compatible = "st,stm32f469-qspi";

	reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;

	reg-names = "qspi", "qspi_mm";

	interrupts = <91>;

	resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;

	clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_qspi0>;



	flash@0 {

		compatible = "jedec,spi-nor";

		reg = <0>;

		spi-rx-bus-width = <4>;

		spi-max-frequency = <108000000>;

		...

	};

};