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Commit c3b5a843 authored by fred gao's avatar fred gao Committed by Zhenyu Wang
Browse files

drm/i915/gvt: Enable gfx virtualiztion for CFL 



Use INTEL_GEN to simplify the code for SKL+ platforms.

v2:
- split the enabling code into final one to identify any regression.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Reviewed-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarFei Jiang <fei.jiang@intel.com>
Signed-off-by: default avatarfred gao <fred.gao@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 5cd02703

drivers/gpu/drm/i915/gvt/cmd_parser.c

+5 −10
Original line number Diff line number Diff line
@@ -901,7 +901,8 @@ static int cmd_reg_handler(struct parser_exec_state *s, 
	 * It's good enough to support initializing mmio by lri command in

	 * vgpu inhibit context on KBL.

	 */

	if (IS_KABYLAKE(s->vgpu->gvt->dev_priv) &&

	if ((IS_KABYLAKE(s->vgpu->gvt->dev_priv)

		|| IS_COFFEELAKE(s->vgpu->gvt->dev_priv)) &&

			intel_gvt_mmio_is_in_ctx(gvt, offset) &&

			!strncmp(cmd, "lri", 3)) {

		intel_gvt_hypervisor_read_gpa(s->vgpu,
@@ -1280,9 +1281,7 @@ static int gen8_check_mi_display_flip(struct parser_exec_state *s, 
	if (!info->async_flip)

		return 0;



	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv)) {

	if (INTEL_GEN(dev_priv) >= 9) {

		stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);

		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &

				GENMASK(12, 10)) >> 10;
@@ -1310,9 +1309,7 @@ static int gen8_update_plane_mmio_from_mi_display_flip( 


	set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),

		      info->surf_val << 12);

	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv)) {

	if (INTEL_GEN(dev_priv) >= 9) {

		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),

			      info->stride_val);

		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
@@ -1336,9 +1333,7 @@ static int decode_mi_display_flip(struct parser_exec_state *s, 


	if (IS_BROADWELL(dev_priv))

		return gen8_decode_mi_display_flip(s, info);

	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv))

	if (INTEL_GEN(dev_priv) >= 9)

		return skl_decode_mi_display_flip(s, info);



	return -ENODEV;

drivers/gpu/drm/i915/gvt/display.c

+8 −4
Original line number Diff line number Diff line
@@ -198,7 +198,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
			SDE_PORTC_HOTPLUG_CPT |

			SDE_PORTD_HOTPLUG_CPT);



	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||

	    IS_COFFEELAKE(dev_priv)) {

		vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |

				SDE_PORTE_HOTPLUG_SPT);

		vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
@@ -273,7 +274,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;

	}



	if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&

	if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||

	     IS_COFFEELAKE(dev_priv)) &&

			intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {

		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;

	}
@@ -453,7 +455,8 @@ void intel_vgpu_clean_display(struct intel_vgpu *vgpu) 
{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;



	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||

	    IS_COFFEELAKE(dev_priv))

		clean_virtual_dp_monitor(vgpu, PORT_D);

	else

		clean_virtual_dp_monitor(vgpu, PORT_B);
@@ -476,7 +479,8 @@ int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) 


	intel_vgpu_init_i2c_edid(vgpu);



	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||

	    IS_COFFEELAKE(dev_priv))

		return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,

						resolution);

	else

drivers/gpu/drm/i915/gvt/dmabuf.c

+1 −3
Original line number Diff line number Diff line
@@ -163,9 +163,7 @@ static struct drm_i915_gem_object *vgpu_create_gem(struct drm_device *dev, 


	obj->read_domains = I915_GEM_DOMAIN_GTT;

	obj->write_domain = 0;

	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv)) {

	if (INTEL_GEN(dev_priv) >= 9) {

		unsigned int tiling_mode = 0;

		unsigned int stride = 0;

drivers/gpu/drm/i915/gvt/fb_decoder.c

+3 −9
Original line number Diff line number Diff line
@@ -151,9 +151,7 @@ static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe, 
	u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask;

	u32 stride = stride_reg;



	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv)) {

	if (INTEL_GEN(dev_priv) >= 9) {

		switch (tiled) {

		case PLANE_CTL_TILED_LINEAR:

			stride = stride_reg * 64;
@@ -217,9 +215,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, 
	if (!plane->enabled)

		return -ENODEV;



	if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv)) {

	if (INTEL_GEN(dev_priv) >= 9) {

		plane->tiled = val & PLANE_CTL_TILED_MASK;

		fmt = skl_format_to_drm(

			val & PLANE_CTL_FORMAT_MASK,
@@ -260,9 +256,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, 
	}



	plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,

		(IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)

		|| IS_BROXTON(dev_priv)) ?

		(INTEL_GEN(dev_priv) >= 9) ?

			(_PRI_PLANE_STRIDE_MASK >> 6) :

				_PRI_PLANE_STRIDE_MASK, plane->bpp);

drivers/gpu/drm/i915/gvt/handlers.c

+8 −9
Original line number Diff line number Diff line
@@ -283,9 +283,7 @@ static int mul_force_wake_write(struct intel_vgpu *vgpu, 
	old = vgpu_vreg(vgpu, offset);

	new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);



	if (IS_SKYLAKE(vgpu->gvt->dev_priv)

		|| IS_KABYLAKE(vgpu->gvt->dev_priv)

		|| IS_BROXTON(vgpu->gvt->dev_priv)) {

	if (INTEL_GEN(vgpu->gvt->dev_priv)  >=  9) {

		switch (offset) {

		case FORCEWAKE_RENDER_GEN9_REG:

			ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
@@ -891,9 +889,7 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 
	write_vreg(vgpu, offset, p_data, bytes);

	data = vgpu_vreg(vgpu, offset);



	if ((IS_SKYLAKE(vgpu->gvt->dev_priv)

		|| IS_KABYLAKE(vgpu->gvt->dev_priv)

		|| IS_BROXTON(vgpu->gvt->dev_priv))

	if ((INTEL_GEN(vgpu->gvt->dev_priv) >= 9)

		&& offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {

		/* SKL DPB/C/D aux ctl register changed */

		return 0;
@@ -1409,7 +1405,8 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 
	switch (cmd) {

	case GEN9_PCODE_READ_MEM_LATENCY:

		if (IS_SKYLAKE(vgpu->gvt->dev_priv)

			 || IS_KABYLAKE(vgpu->gvt->dev_priv)) {

			 || IS_KABYLAKE(vgpu->gvt->dev_priv)

			 || IS_COFFEELAKE(vgpu->gvt->dev_priv)) {

			/**

			 * "Read memory latency" command on gen9.

			 * Below memory latency values are read
@@ -1433,7 +1430,8 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 
		break;

	case SKL_PCODE_CDCLK_CONTROL:

		if (IS_SKYLAKE(vgpu->gvt->dev_priv)

			 || IS_KABYLAKE(vgpu->gvt->dev_priv))

			 || IS_KABYLAKE(vgpu->gvt->dev_priv)

			 || IS_COFFEELAKE(vgpu->gvt->dev_priv))

			*data0 = SKL_CDCLK_READY_FOR_CHANGE;

		break;

	case GEN6_PCODE_READ_RC6VIDS:
@@ -3304,7 +3302,8 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 
		if (ret)

			goto err;

	} else if (IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv)) {

		|| IS_KABYLAKE(dev_priv)

		|| IS_COFFEELAKE(dev_priv)) {

		ret = init_broadwell_mmio_info(gvt);

		if (ret)

			goto err;