Loading qcom/shima.dtsi +10 −0 Original line number Diff line number Diff line Loading @@ -6,6 +6,7 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,videocc-shima.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/qcom,ipcc.h> / { model = "Qualcomm Technologies, Inc. Shima"; Loading Loading @@ -494,6 +495,15 @@ #clock-cells = <1>; #reset-cells = <1>; }; ipcc_mproc: qcom,ipcc@408000 { compatible = "qcom,ipcc"; reg = <0x408000 0x1000>; interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <3>; #mbox-cells = <2>; }; }; #include "shima-pinctrl.dtsi" Loading Loading
qcom/shima.dtsi +10 −0 Original line number Diff line number Diff line Loading @@ -6,6 +6,7 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,videocc-shima.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/qcom,ipcc.h> / { model = "Qualcomm Technologies, Inc. Shima"; Loading Loading @@ -494,6 +495,15 @@ #clock-cells = <1>; #reset-cells = <1>; }; ipcc_mproc: qcom,ipcc@408000 { compatible = "qcom,ipcc"; reg = <0x408000 0x1000>; interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <3>; #mbox-cells = <2>; }; }; #include "shima-pinctrl.dtsi" Loading