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Commit c39c24c1 authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Jerome Brunet
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clk: meson: meson8b: add the cts_mclk_i958 clocks 



Add the SPDIF master clock also referred as cts_mclk_i958. The setup for
this clock is identical to GXBB, so this ports commit 3c277c24
("clk: meson: gxbb: add cts_mclk_i958") to the Meson8/Meson8b/Meson8m2
clock driver.

Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent f278f05e

drivers/clk/meson/meson8b.c

+65 −0
Original line number Diff line number Diff line
@@ -2206,6 +2206,59 @@ static struct clk_regmap meson8b_cts_amclk = { 
	},

};



/* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */

static const char * const meson8b_cts_mclk_i958_parent_names[] = {

	"mpll0", "mpll1", "mpll2"

};



static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 };



static struct clk_regmap meson8b_cts_mclk_i958_sel = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_AUD_CLK_CNTL2,

		.mask = 0x3,

		.shift = 25,

		.table = meson8b_cts_mclk_i958_mux_table,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data) {

		.name = "cts_mclk_i958_sel",

		.ops = &clk_regmap_mux_ops,

		.parent_names = meson8b_cts_mclk_i958_parent_names,

		.num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_names),

	},

};



static struct clk_regmap meson8b_cts_mclk_i958_div = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_AUD_CLK_CNTL2,

		.shift = 16,

		.width = 8,

		.flags = CLK_DIVIDER_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data) {

		.name = "cts_mclk_i958_div",

		.ops = &clk_regmap_divider_ops,

		.parent_names = (const char *[]){ "cts_mclk_i958_sel" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap meson8b_cts_mclk_i958 = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_AUD_CLK_CNTL2,

		.bit_idx = 24,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cts_mclk_i958",

		.ops = &clk_regmap_gate_ops,

		.parent_names = (const char *[]){ "cts_mclk_i958_div" },

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



/* Everything Else (EE) domain gates */



static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
@@ -2488,6 +2541,9 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = { 
		[CLKID_CTS_AMCLK_SEL]	    = &meson8b_cts_amclk_sel.hw,

		[CLKID_CTS_AMCLK_DIV]	    = &meson8b_cts_amclk_div.hw,

		[CLKID_CTS_AMCLK]	    = &meson8b_cts_amclk.hw,

		[CLKID_CTS_MCLK_I958_SEL]   = &meson8b_cts_mclk_i958_sel.hw,

		[CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,

		[CLKID_CTS_MCLK_I958]	    = &meson8b_cts_mclk_i958.hw,

		[CLK_NR_CLKS]		    = NULL,

	},

	.num = CLK_NR_CLKS,
@@ -2700,6 +2756,9 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { 
		[CLKID_CTS_AMCLK_SEL]	    = &meson8b_cts_amclk_sel.hw,

		[CLKID_CTS_AMCLK_DIV]	    = &meson8b_cts_amclk_div.hw,

		[CLKID_CTS_AMCLK]	    = &meson8b_cts_amclk.hw,

		[CLKID_CTS_MCLK_I958_SEL]   = &meson8b_cts_mclk_i958_sel.hw,

		[CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,

		[CLKID_CTS_MCLK_I958]	    = &meson8b_cts_mclk_i958.hw,

		[CLK_NR_CLKS]		    = NULL,

	},

	.num = CLK_NR_CLKS,
@@ -2914,6 +2973,9 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = { 
		[CLKID_CTS_AMCLK_SEL]	    = &meson8b_cts_amclk_sel.hw,

		[CLKID_CTS_AMCLK_DIV]	    = &meson8b_cts_amclk_div.hw,

		[CLKID_CTS_AMCLK]	    = &meson8b_cts_amclk.hw,

		[CLKID_CTS_MCLK_I958_SEL]   = &meson8b_cts_mclk_i958_sel.hw,

		[CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,

		[CLKID_CTS_MCLK_I958]	    = &meson8b_cts_mclk_i958.hw,

		[CLK_NR_CLKS]		    = NULL,

	},

	.num = CLK_NR_CLKS,
@@ -3106,6 +3168,9 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { 
	&meson8b_cts_amclk,

	&meson8b_cts_amclk_sel,

	&meson8b_cts_amclk_div,

	&meson8b_cts_mclk_i958_sel,

	&meson8b_cts_mclk_i958_div,

	&meson8b_cts_mclk_i958,

};



static const struct meson8b_clk_reset_line {

drivers/clk/meson/meson8b.h

+4 −1
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 
#define HHI_MPEG_CLK_CNTL		0x174 /* 0x5d offset in data sheet */

#define HHI_AUD_CLK_CNTL		0x178 /* 0x5e offset in data sheet */

#define HHI_VID_CLK_CNTL		0x17c /* 0x5f offset in data sheet */

#define HHI_AUD_CLK_CNTL2		0x190 /* 0x64 offset in data sheet */

#define HHI_VID_CLK_CNTL2		0x194 /* 0x65 offset in data sheet */

#define HHI_VID_DIVIDER_CNTL		0x198 /* 0x66 offset in data sheet */

#define HHI_SYS_CPU_CLK_CNTL0		0x19c /* 0x67 offset in data sheet */
@@ -174,8 +175,10 @@ 
#define CLKID_VDEC_HEVC_EN	205

#define CLKID_CTS_AMCLK_SEL	207

#define CLKID_CTS_AMCLK_DIV	208

#define CLKID_CTS_MCLK_I958_SEL	210

#define CLKID_CTS_MCLK_I958_DIV	211



#define CLK_NR_CLKS		210

#define CLK_NR_CLKS		213



/*

 * include the CLKID and RESETID that have