Merge commit 'f9fe1c12' into for-next

Required properties:

- compatible: should contain one of "brcm,genet-v1", "brcm,genet-v2",

  "brcm,genet-v3", "brcm,genet-v4".

  "brcm,genet-v3", "brcm,genet-v4", "brcm,genet-v5".

- reg: address and length of the register set for the device

- interrupts: must be two cells, the first cell is the general purpose

  interrupt line, while the second cell is the interrupt for the ring

  RX and TX queues operating in ring mode

- interrupts and/or interrupts-extended: must be two cells, the first cell

  is the general purpose interrupt line, while the second cell is the

  interrupt for the ring RX and TX queues operating in ring mode.  An

  optional third interrupt cell for Wake-on-LAN can be specified.

  See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt

  for information on the property specifics.

- phy-mode: see ethernet.txt file in the same directory

- #address-cells: should be 1

- #size-cells: should be 1

Required child nodes:

- mdio bus node: this node should always be present regarless of the PHY

- mdio bus node: this node should always be present regardless of the PHY

  configuration of the GENET instance

MDIO bus node required properties:

- compatible: should contain one of "brcm,genet-mdio-v1", "brcm,genet-mdio-v2"

  "brcm,genet-mdio-v3", "brcm,genet-mdio-v4", the version has to match the

  parent node compatible property (e.g: brcm,genet-v4 pairs with

  brcm,genet-mdio-v4)

  "brcm,genet-mdio-v3", "brcm,genet-mdio-v4", "brcm,genet-mdio-v5", the version

  has to match the parent node compatible property (e.g: brcm,genet-v4 pairs

  with brcm,genet-mdio-v4)

- reg: address and length relative to the parent node base register address

- #address-cells: address cell for MDIO bus addressing, should be 1

- #size-cells: size of the cells for MDIO bus addressing, should be 0

Required properties:

- compatible: should one from "brcm,genet-mdio-v1", "brcm,genet-mdio-v2",

  "brcm,genet-mdio-v3", "brcm,genet-mdio-v4" or "brcm,unimac-mdio"

- reg: address and length of the regsiter set for the device, first one is the

  "brcm,genet-mdio-v3", "brcm,genet-mdio-v4", "brcm,genet-mdio-v5" or

  "brcm,unimac-mdio"

- reg: address and length of the register set for the device, first one is the

  base register, and the second one is optional and for indirect accesses to

  larger than 16-bits MDIO transactions

- reg-names: name(s) of the register must be "mdio" and optional "mdio_indir_rw"

* Marvell Armada 375 Ethernet Controller (PPv2)

* Marvell Armada 375 Ethernet Controller (PPv2.1)

  Marvell Armada 7K/8K Ethernet Controller (PPv2.2)

Required properties:

- compatible: should be "marvell,armada-375-pp2"

- compatible: should be one of:

    "marvell,armada-375-pp2"

    "marvell,armada-7k-pp2"

- reg: addresses and length of the register sets for the device.

  Must contain the following register sets:

  For "marvell,armada-375-pp2", must contain the following register

  sets:

	- common controller registers

	- LMS registers

  In addition, at least one port register set is required.

- clocks: a pointer to the reference clocks for this device, consequently:

	- main controller clock

	- GOP clock

- clock-names: names of used clocks, must be "pp_clk" and "gop_clk".

	- one register area per Ethernet port

  For "marvell,armada-7k-pp2", must contain the following register

  sets:

	- packet processor registers

	- networking interfaces registers

- clocks: pointers to the reference clocks for this device, consequently:

	- main controller clock (for both armada-375-pp2 and armada-7k-pp2)

	- GOP clock (for both armada-375-pp2 and armada-7k-pp2)

	- MG clock (only for armada-7k-pp2)

- clock-names: names of used clocks, must be "pp_clk", "gop_clk" and

  "mg_clk" (the latter only for armada-7k-pp2).

The ethernet ports are represented by subnodes. At least one port is

required.

Required properties (port):

- interrupts: interrupt for the port

- port-id: should be '0' or '1' for ethernet ports, and '2' for the

           loopback port

- port-id: ID of the port from the MAC point of view

- gop-port-id: only for marvell,armada-7k-pp2, ID of the port from the

  GOP (Group Of Ports) point of view. This ID is used to index the

  per-port registers in the second register area.

- phy-mode: See ethernet.txt file in the same directory

Optional properties (port):

- phy: a phandle to a phy node defining the PHY address (as the reg

  property, a single integer).

Example:

Example for marvell,armada-375-pp2:

ethernet@f0000 {

	compatible = "marvell,armada-375-pp2";

		phy-mode = "gmii";

	};

};

Example for marvell,armada-7k-pp2:

cpm_ethernet: ethernet@0 {

	compatible = "marvell,armada-7k-pp22";

	reg = <0x0 0x100000>, <0x129000 0xb000>;

	clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;

	clock-names = "pp_clk", "gop_clk", "gp_clk";

	eth0: eth0 {

		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

		port-id = <0>;

		gop-port-id = <0>;

	};

	eth1: eth1 {

		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;

		port-id = <1>;

		gop-port-id = <2>;

	};

	eth2: eth2 {

		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;

		port-id = <2>;

		gop-port-id = <3>;

	};

};

  clocks may be specified in derived bindings.

- clock-names: One name for each entry in the clocks property, the

  first one should be "stmmaceth" and the second one should be "pclk".

- clk_ptp_ref: this is the PTP reference clock; in case of the PTP is

  available this clock is used for programming the Timestamp Addend Register.

  If not passed then the system clock will be used and this is fine on some

- ptp_ref: this is the PTP reference clock; in case of the PTP is available

  this clock is used for programming the Timestamp Addend Register. If not

  passed then the system clock will be used and this is fine on some

  platforms.

- tx-fifo-depth: See ethernet.txt file in the same directory

- rx-fifo-depth: See ethernet.txt file in the same directory

	- snps,mb: mixed-burst

	- snps,rb: rebuild INCRx Burst

- mdio: with compatible = "snps,dwmac-mdio", create and register mdio bus.

- Multiple RX Queues parameters: below the list of all the parameters to

				 configure the multiple RX queues:

	- snps,rx-queues-to-use: number of RX queues to be used in the driver

	- Choose one of these RX scheduling algorithms:

		- snps,rx-sched-sp: Strict priority

		- snps,rx-sched-wsp: Weighted Strict priority

	- For each RX queue

		- Choose one of these modes:

			- snps,dcb-algorithm: Queue to be enabled as DCB

			- snps,avb-algorithm: Queue to be enabled as AVB

		- snps,map-to-dma-channel: Channel to map

		- Specifiy specific packet routing:

			- snps,route-avcp: AV Untagged Control packets

			- snps,route-ptp: PTP Packets

			- snps,route-dcbcp: DCB Control Packets

			- snps,route-up: Untagged Packets

			- snps,route-multi-broad: Multicast & Broadcast Packets

		- snps,priority: RX queue priority (Range: 0x0 to 0xF)

- Multiple TX Queues parameters: below the list of all the parameters to

				 configure the multiple TX queues:

	- snps,tx-queues-to-use: number of TX queues to be used in the driver

	- Choose one of these TX scheduling algorithms:

		- snps,tx-sched-wrr: Weighted Round Robin

		- snps,tx-sched-wfq: Weighted Fair Queuing

		- snps,tx-sched-dwrr: Deficit Weighted Round Robin

		- snps,tx-sched-sp: Strict priority

	- For each TX queue

		- snps,weight: TX queue weight (if using a DCB weight algorithm)

		- Choose one of these modes:

			- snps,dcb-algorithm: TX queue will be working in DCB

			- snps,avb-algorithm: TX queue will be working in AVB

		- Configure Credit Base Shaper (if AVB Mode selected):

			- snps,send_slope: enable Low Power Interface

			- snps,idle_slope: unlock on WoL

			- snps,high_credit: max write outstanding req. limit

			- snps,low_credit: max read outstanding req. limit

		- snps,priority: TX queue priority (Range: 0x0 to 0xF)

Examples:

	stmmac_axi_setup: stmmac-axi-config {

		snps,blen = <256 128 64 32 0 0 0>;

	};

	mtl_rx_setup: rx-queues-config {

		snps,rx-queues-to-use = <1>;

		snps,rx-sched-sp;

		queue0 {

			snps,dcb-algorithm;

			snps,map-to-dma-channel = <0x0>;

			snps,priority = <0x0>;

		};

	};

	mtl_tx_setup: tx-queues-config {

		snps,tx-queues-to-use = <2>;

		snps,tx-sched-wrr;

		queue0 {

			snps,weight = <0x10>;

			snps,dcb-algorithm;

			snps,priority = <0x0>;

		};

		queue1 {

			snps,avb-algorithm;

			snps,send_slope = <0x1000>;

			snps,idle_slope = <0x1000>;

			snps,high_credit = <0x3E800>;

			snps,low_credit = <0xFFC18000>;

			snps,priority = <0x1>;

		};

	};

	gmac0: ethernet@e0800000 {

		compatible = "st,spear600-gmac";

		reg = <0xe0800000 0x8000>;

			phy1: ethernet-phy@0 {

			};

		};

		snps,mtl-rx-config = <&mtl_rx_setup>;

		snps,mtl-tx-config = <&mtl_tx_setup>;

	};

	0 - disabled

	1 - enabled

fib_multipath_hash_policy - INTEGER

	Controls which hash policy to use for multipath routes. Only valid

	for kernels built with CONFIG_IP_ROUTE_MULTIPATH enabled.

	Default: 0 (Layer 3)

	Possible values:

	0 - Layer 3

	1 - Layer 4

route/max_size - INTEGER

	Maximum number of routes allowed in the kernel.  Increase

	this when using large numbers of interfaces and/or routes.

	building larger TSO frames.

	Default: 3

tcp_tw_recycle - BOOLEAN

	Enable fast recycling TIME-WAIT sockets. Default value is 0.

	It should not be changed without advice/request of technical

	experts.

tcp_tw_reuse - BOOLEAN

	Allow to reuse TIME-WAIT sockets for new connections when it is

	safe from protocol viewpoint. Default value is 0.