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Commit c3143967 authored by Tigran Tadevosyan's avatar Tigran Tadevosyan Committed by Russell King
Browse files

ARM: 8856/1: NOMMU: Fix CCR register faulty initialization when MPU is disabled 



When CONFIG_ARM_MPU is not defined, the base address of v7M SCB register
is not initialized with correct value. This prevents enabling I/D caches
when the L1 cache poilcy is applied in kernel.

Fixes: 3c241210 ("ARM: 8756/1: NOMMU: Postpone MPU activation till __after_proc_init")
Signed-off-by: default avatarTigran Tadevosyan <tigran.tadevosyan@arm.com>
Signed-off-by: default avatarVladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
parent 50362162

arch/arm/kernel/head-nommu.S

+1 −1
Original line number Diff line number Diff line
@@ -133,9 +133,9 @@ __secondary_data: 
 */

	.text

__after_proc_init:

#ifdef CONFIG_ARM_MPU

M_CLASS(movw	r12, #:lower16:BASEADDR_V7M_SCB)

M_CLASS(movt	r12, #:upper16:BASEADDR_V7M_SCB)

#ifdef CONFIG_ARM_MPU

M_CLASS(ldr	r3, [r12, 0x50])

AR_CLASS(mrc	p15, 0, r3, c0, c1, 4)          @ Read ID_MMFR0

	and	r3, r3, #(MMFR0_PMSA)           @ PMSA field