Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c2ef6bea authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Add stub interconnect devices for sdxlemur"

parents c0fbc629 820c448e
Loading
Loading
Loading
Loading
+23 −0
Original line number Diff line number Diff line
Qualcomm Technologies, Inc. SDXLEMUR Network-On-Chip interconnect driver binding
--------------------------------------------------------------------------------

SDXLEMUR interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.

Required properties :
- compatible : shall contain only one of the following:
			"qcom,sdxlemur-system_noc",
			"qcom,sdxlemur-mem_noc",
			"qcom,sdxlemur-mc_virt",
- #interconnect-cells : should contain 1

Examples:

system_noc: interconnect@1620000 {
	compatible = "qcom,sdxlemur-system_noc";
	interconnect-cells = <1>;
};
+16 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@
#include <dt-bindings/clock/qcom,gcc-sdxlemur.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sdxlemur.h>

/ {
	#address-cells = <1>;
@@ -266,6 +267,21 @@
		reg = <0x117004 0x4>;
		regulator-name = "gcc_usb30_gdsc";
	};

	system_noc: interconnect@1620000 {
		compatible = "qcom,sdxlemur-system_noc";
		#interconnect-cells = <1>;
	};

	mem_noc: interconnect@9680000 {
		compatible = "qcom,sdxlemur-mem_noc";
		#interconnect-cells = <1>;
	};

	mc_virt: interconnect {
		compatible = "qcom,sdxlemur-mc_virt";
		#interconnect-cells = <1>;
	};
};

#include "sdxlemur-pinctrl.dtsi"