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Commit c2d3db8c authored by Michael Chan's avatar Michael Chan Committed by David S. Miller
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[BNX2]: Add delay before reading firmware version. 



The management firmware may still be loading during bnx2_init_one()
because of the D3hot -> D0 transition and the firmware version may
not be available without waiting a bit.

Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e30372c9

drivers/net/bnx2.c

+12 −4
Original line number Original line Diff line number Diff line
@@ -4143,10 +4143,6 @@ bnx2_init_chip(struct bnx2 *bp) 




	REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);

	REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);





	if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &

	    BNX2_PORT_FEATURE_ASF_ENABLED)

		bp->flags |= ASF_ENABLE_FLAG;



	/* Initialize the receive filter. */

	/* Initialize the receive filter. */

	bnx2_set_rx_mode(bp->dev);

	bnx2_set_rx_mode(bp->dev);
@@ -6645,6 +6641,18 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) 
		if (i != 2)

		if (i != 2)

			bp->fw_version[j++] = '.';

			bp->fw_version[j++] = '.';

	}

	}

	if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &

	    BNX2_PORT_FEATURE_ASF_ENABLED) {

		bp->flags |= ASF_ENABLE_FLAG;



		for (i = 0; i < 30; i++) {

			reg = REG_RD_IND(bp, bp->shmem_base +

					     BNX2_BC_STATE_CONDITION);

			if (reg & BNX2_CONDITION_MFW_RUN_MASK)

				break;

			msleep(10);

		}

	}

	reg = REG_RD_IND(bp, bp->shmem_base + BNX2_BC_STATE_CONDITION);

	reg = REG_RD_IND(bp, bp->shmem_base + BNX2_BC_STATE_CONDITION);

	reg &= BNX2_CONDITION_MFW_RUN_MASK;

	reg &= BNX2_CONDITION_MFW_RUN_MASK;

	if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&

	if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&