Loading bindings/pinctrl/qcom,yupik-pinctrl.txt +5 −0 Original line number Diff line number Diff line Loading @@ -45,6 +45,11 @@ YUPIK platform. Value type: <phandle> Definition: A phandle to the wakeup interrupt controller for the SoC. - qcom,tlmm-mpm-wake-control: Usage: optional Value type: <bool> Definition: provide mpm wake control capability for a pin. Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. Loading qcom/yupik-pinctrl.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,7 @@ interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>; qcom,tlmm-mpm-wake-control; qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { qupv3_se0_i2c_active: qupv3_se0_i2c_active { Loading Loading
bindings/pinctrl/qcom,yupik-pinctrl.txt +5 −0 Original line number Diff line number Diff line Loading @@ -45,6 +45,11 @@ YUPIK platform. Value type: <phandle> Definition: A phandle to the wakeup interrupt controller for the SoC. - qcom,tlmm-mpm-wake-control: Usage: optional Value type: <bool> Definition: provide mpm wake control capability for a pin. Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. Loading
qcom/yupik-pinctrl.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,7 @@ interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>; qcom,tlmm-mpm-wake-control; qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { qupv3_se0_i2c_active: qupv3_se0_i2c_active { Loading