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Commit c2a48e09 authored by Jagadeesh Kona's avatar Jagadeesh Kona
Browse files

ARM: dts: msm: Update GCC clock node and GDSC for SHIMA 

Update the global clock controller node and the corresponding GDSC's.

Change-Id: I32073b67961e5c023720c41ebe2ccd044c2bb97a
parent b4079659

qcom/shima-gdsc.dtsi

+9 −9
Original line number Diff line number Diff line 
&soc {

	/* GDSCs in GCC */

	gcc_pcie_0_gdsc: qcom,gdsc@16b004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x16b004 0x4>;

		regulator-name = "gcc_pcie_0_gdsc";

		status = "disabled";

	};



	gcc_pcie_1_gdsc: qcom,gdsc@18d004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x18d004 0x4>;

		regulator-name = "gcc_pcie_1_gdsc";

		status = "disabled";

	};



	gcc_ufs_phy_gdsc: qcom,gdsc@177004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x177004 0x4>;

		regulator-name = "gcc_ufs_phy_gdsc";

		status = "disabled";

	};



	gcc_usb30_prim_gdsc: qcom,gdsc@10f004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x10f004 0x4>;

		regulator-name = "gcc_usb30_prim_gdsc";

		status = "disabled";

	};



	hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@17d05c {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x17d05c 0x4>;

		regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";

		qcom,gds-timeout = <500>;
@@ -38,7 +38,7 @@ 
	};



	hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x17d058 0x4>;

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";

		qcom,gds-timeout = <500>;
@@ -47,7 +47,7 @@ 
	};



	hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x17d054 0x4>;

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc";

		qcom,gds-timeout = <500>;
@@ -56,7 +56,7 @@ 
	};



	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x17d050 0x4>;

		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";

		qcom,gds-timeout = <500>;
@@ -65,7 +65,7 @@ 
	};



	hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@17d060 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0x17d060 0x4>;

		regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";

		qcom,gds-timeout = <500>;

qcom/shima-rumi.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -98,3 +98,7 @@ 
&qupv3_se13_2uart {

	qcom,rumi_platform;

};



&gcc {

	clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>;

};

qcom/shima.dtsi

+30 −3
Original line number Diff line number Diff line
@@ -536,6 +536,27 @@ 
			clock-output-names = "chip_sleep_clk";

			#clock-cells = <0>;

		};



		pcie_0_pipe_clk: pcie-0-pipe-clk {

			compatible = "fixed-clock";

			clock-frequency = <1000>;

			clock-output-names = "pcie_0_pipe_clk";

			#clock-cells = <0>;

		};



		pcie_1_pipe_clk: pcie-1-pipe-clk {

			compatible = "fixed-clock";

			clock-frequency = <1000>;

			clock-output-names = "pcie_1_pipe_clk";

			#clock-cells = <0>;

		};



		usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {

			compatible = "fixed-clock";

			clock-frequency = <1000>;

			clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";

			#clock-cells = <0>;

		};

	};



	aopcc: qcom,aopcc {
@@ -545,9 +566,15 @@ 
		#reset-cells = <1>;

	};



	gcc: qcom,gcc@100000 {

		compatible = "qcom,dummycc";

		clock-output-names = "gcc_clocks";

	gcc: clock-controller@100000 {

		compatible = "qcom,shima-gcc", "syscon";

		reg = <0x100000 0x1f0000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;

		clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,

			<&sleep_clk>;

		clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};