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Commit c26d4219 authored by David Daney's avatar David Daney Committed by Ralf Baechle
Browse files

MIPS: Handle OCTEON BBIT instructions in FPU emulator. 



The branch emulation needs to handle the OCTEON BBIT instructions,
otherwise we get SIGILL instead of emulation.

Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5726/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent e5d081f4

arch/mips/math-emu/cp1emu.c

+26 −0
Original line number Diff line number Diff line
@@ -803,6 +803,32 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 
				dec_insn.next_pc_inc;

		return 1;

		break;

#ifdef CONFIG_CPU_CAVIUM_OCTEON

	case lwc2_op: /* This is bbit0 on Octeon */

		if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)

			*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);

		else

			*contpc = regs->cp0_epc + 8;

		return 1;

	case ldc2_op: /* This is bbit032 on Octeon */

		if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)

			*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);

		else

			*contpc = regs->cp0_epc + 8;

		return 1;

	case swc2_op: /* This is bbit1 on Octeon */

		if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))

			*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);

		else

			*contpc = regs->cp0_epc + 8;

		return 1;

	case sdc2_op: /* This is bbit132 on Octeon */

		if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))

			*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);

		else

			*contpc = regs->cp0_epc + 8;

		return 1;

#endif

	case cop0_op:

	case cop1_op:

	case cop2_op: