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Commit c245d94e authored by Rayagonda Kokatanur's avatar Rayagonda Kokatanur Committed by Wolfram Sang
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i2c: iproc: Add multi byte read-write support for slave mode 



Add multiple byte read-write support for slave mode.

Signed-off-by: default avatarRayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Signed-off-by: default avatarSrinath Mannam <srinath.mannam@broadcom.com>
Reviewed-by: default avatarRay Jui <ray.jui@broadcom.com>
Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
parent a4b5363a

drivers/i2c/busses/i2c-bcm-iproc.c

+53 −64
Original line number Diff line number Diff line
@@ -165,12 +165,6 @@ enum i2c_slave_read_status { 
	I2C_SLAVE_RX_END,

};



enum i2c_slave_xfer_dir {

	I2C_SLAVE_DIR_READ = 0,

	I2C_SLAVE_DIR_WRITE,

	I2C_SLAVE_DIR_NONE,

};



enum bus_speed_index {

	I2C_SPD_100K = 0,

	I2C_SPD_400K,
@@ -203,7 +197,6 @@ struct bcm_iproc_i2c_dev { 
	struct i2c_msg *msg;



	struct i2c_client *slave;

	enum i2c_slave_xfer_dir xfer_dir;



	/* bytes that have been transferred */

	unsigned int tx_bytes;
@@ -219,7 +212,8 @@ struct bcm_iproc_i2c_dev { 
		| BIT(IS_M_RX_THLD_SHIFT))



#define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\

		| BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT))

		| BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\

		| BIT(IS_S_TX_UNDERRUN_SHIFT))



static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);

static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
@@ -297,15 +291,11 @@ static void bcm_iproc_i2c_slave_init( 
	/* clear all pending slave interrupts */

	iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);



	/* Enable interrupt register for any READ event */

	val = BIT(IE_S_RD_EVENT_SHIFT);

	/* Enable interrupt register to indicate a valid byte in receive fifo */

	val |= BIT(IE_S_RX_EVENT_SHIFT);

	val = BIT(IE_S_RX_EVENT_SHIFT);

	/* Enable interrupt register for the Slave BUSY command */

	val |= BIT(IE_S_START_BUSY_SHIFT);

	iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);



	iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE;

}



static void bcm_iproc_i2c_check_slave_status(
@@ -314,8 +304,11 @@ static void bcm_iproc_i2c_check_slave_status( 
	u32 val;



	val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);

	val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;

	/* status is valid only when START_BUSY is cleared after it was set */

	if (val & BIT(S_CMD_START_BUSY_SHIFT))

		return;



	val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;

	if (val == S_CMD_STATUS_TIMEOUT) {

		dev_err(iproc_i2c->device, "slave random stretch time timeout\n");
@@ -329,68 +322,64 @@ static void bcm_iproc_i2c_check_slave_status( 
static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,

				    u32 status)

{

	u8 value;

	u32 val;

	u32 rd_status;

	u32 tmp;

	u8 value, rx_status;



	/* Start of transaction. check address and populate the direction */

	if (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_NONE) {

		tmp = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);

		rd_status = (tmp >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;

		/* This condition checks whether the request is a new request */

		if (((rd_status == I2C_SLAVE_RX_START) &&

			(status & BIT(IS_S_RX_EVENT_SHIFT))) ||

			((rd_status == I2C_SLAVE_RX_END) &&

			(status & BIT(IS_S_RD_EVENT_SHIFT)))) {



			/* Last bit is W/R bit.

			 * If 1 then its a read request(by master).

			 */

			iproc_i2c->xfer_dir = tmp & SLAVE_READ_WRITE_BIT_MASK;

			if (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_WRITE)

				i2c_slave_event(iproc_i2c->slave,

					I2C_SLAVE_READ_REQUESTED, &value);

			else

	/* Slave RX byte receive */

	if (status & BIT(IS_S_RX_EVENT_SHIFT)) {

		val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);

		rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;

		if (rx_status == I2C_SLAVE_RX_START) {

			/* Start of SMBUS for Master write */

			i2c_slave_event(iproc_i2c->slave,

					I2C_SLAVE_WRITE_REQUESTED, &value);

		}

	}



	/* read request from master */

	if ((status & BIT(IS_S_RD_EVENT_SHIFT)) &&

		(iproc_i2c->xfer_dir == I2C_SLAVE_DIR_WRITE)) {

			val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);

			value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);

			i2c_slave_event(iproc_i2c->slave,

			I2C_SLAVE_READ_PROCESSED, &value);

					I2C_SLAVE_WRITE_RECEIVED, &value);

		} else if (status & BIT(IS_S_RD_EVENT_SHIFT)) {

			/* Start of SMBUS for Master Read */

			i2c_slave_event(iproc_i2c->slave,

					I2C_SLAVE_READ_REQUESTED, &value);

			iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);



			val = BIT(S_CMD_START_BUSY_SHIFT);

			iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);

	}



	/* write request from master */

	if ((status & BIT(IS_S_RX_EVENT_SHIFT)) &&

		(iproc_i2c->xfer_dir == I2C_SLAVE_DIR_READ)) {

		val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);

		/* Its a write request by Master to Slave.

		 * We read data present in receive FIFO

			/*

			 * Enable interrupt for TX FIFO becomes empty and

			 * less than PKT_LENGTH bytes were output on the SMBUS

			 */

			val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);

			val |= BIT(IE_S_TX_UNDERRUN_SHIFT);

			iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);

		} else {

			/* Master write other than start */

			value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);

			i2c_slave_event(iproc_i2c->slave,

					I2C_SLAVE_WRITE_RECEIVED, &value);

		}

	} else if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {

		/* Master read other than start */

		i2c_slave_event(iproc_i2c->slave,

				I2C_SLAVE_READ_PROCESSED, &value);



		/* check the status for the last byte of the transaction */

		rd_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;

		if (rd_status == I2C_SLAVE_RX_END)

			iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE;



		dev_dbg(iproc_i2c->device, "\nread value = 0x%x\n", value);

		iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);

		val = BIT(S_CMD_START_BUSY_SHIFT);

		iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);

	}



	/* Stop */

	if (status & BIT(IS_S_START_BUSY_SHIFT)) {

		i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);

		iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE;

		/*

		 * Enable interrupt for TX FIFO becomes empty and

		 * less than PKT_LENGTH bytes were output on the SMBUS

		 */

		val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);

		val &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);

		iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);

	}



	/* clear interrupt status */