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Commit c1df1925 authored by Csókás Bence's avatar Csókás Bence Committed by Greg Kroah-Hartman
Browse files

net: fec: Refactor: #define magic constants 



[ Upstream commit ff049886671ccd4e624a30ec464cb20e4c39a313 ]

Add defines for bits of ECR, RCR control registers, TX watermark etc.

Signed-off-by: default avatarCsókás Bence <csokas.bence@prolan.hu>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20240212153717.10023-1-csokas.bence@prolan.hu


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
Stable-dep-of: c32fe1986f27 ("net: fec: Fix FEC_ECR_EN1588 being cleared on link-down")
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent b289ebb0

drivers/net/ethernet/freescale/fec_main.c

+30 −16
Original line number Diff line number Diff line
@@ -223,8 +223,8 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 
#define PKT_MINBUF_SIZE		64



/* FEC receive acceleration */

#define FEC_RACC_IPDIS		(1 << 1)

#define FEC_RACC_PRODIS		(1 << 2)

#define FEC_RACC_IPDIS		BIT(1)

#define FEC_RACC_PRODIS		BIT(2)

#define FEC_RACC_SHIFT16	BIT(7)

#define FEC_RACC_OPTIONS	(FEC_RACC_IPDIS | FEC_RACC_PRODIS)
@@ -256,8 +256,23 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); 
#define FEC_MMFR_TA		(2 << 16)

#define FEC_MMFR_DATA(v)	(v & 0xffff)

/* FEC ECR bits definition */

#define FEC_ECR_MAGICEN		(1 << 2)

#define FEC_ECR_SLEEP		(1 << 3)

#define FEC_ECR_RESET           BIT(0)

#define FEC_ECR_ETHEREN         BIT(1)

#define FEC_ECR_MAGICEN         BIT(2)

#define FEC_ECR_SLEEP           BIT(3)

#define FEC_ECR_EN1588          BIT(4)

#define FEC_ECR_BYTESWP         BIT(8)

/* FEC RCR bits definition */

#define FEC_RCR_LOOP            BIT(0)

#define FEC_RCR_HALFDPX         BIT(1)

#define FEC_RCR_MII             BIT(2)

#define FEC_RCR_PROMISC         BIT(3)

#define FEC_RCR_BC_REJ          BIT(4)

#define FEC_RCR_FLOWCTL         BIT(5)

#define FEC_RCR_RMII            BIT(8)

#define FEC_RCR_10BASET         BIT(9)

/* TX WMARK bits */

#define FEC_TXWMRK_STRFWD       BIT(8)



#define FEC_MII_TIMEOUT		30000 /* us */
@@ -953,7 +968,7 @@ fec_restart(struct net_device *ndev) 
	u32 val;

	u32 temp_mac[2];

	u32 rcntl = OPT_FRAME_SIZE | 0x04;

	u32 ecntl = 0x2; /* ETHEREN */

	u32 ecntl = FEC_ECR_ETHEREN;



	/* Whack a reset.  We should wait for this.

	 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
@@ -1029,18 +1044,18 @@ fec_restart(struct net_device *ndev) 
		    fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)

			rcntl |= (1 << 6);

		else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)

			rcntl |= (1 << 8);

			rcntl |= FEC_RCR_RMII;

		else

			rcntl &= ~(1 << 8);

			rcntl &= ~FEC_RCR_RMII;



		/* 1G, 100M or 10M */

		if (ndev->phydev) {

			if (ndev->phydev->speed == SPEED_1000)

				ecntl |= (1 << 5);

			else if (ndev->phydev->speed == SPEED_100)

				rcntl &= ~(1 << 9);

				rcntl &= ~FEC_RCR_10BASET;

			else

				rcntl |= (1 << 9);

				rcntl |= FEC_RCR_10BASET;

		}

	} else {

#ifdef FEC_MIIGSK_ENR
@@ -1099,13 +1114,13 @@ fec_restart(struct net_device *ndev) 


	if (fep->quirks & FEC_QUIRK_ENET_MAC) {

		/* enable ENET endian swap */

		ecntl |= (1 << 8);

		ecntl |= FEC_ECR_BYTESWP;

		/* enable ENET store and forward mode */

		writel(1 << 8, fep->hwp + FEC_X_WMRK);

		writel(FEC_TXWMRK_STRFWD, fep->hwp + FEC_X_WMRK);

	}



	if (fep->bufdesc_ex)

		ecntl |= (1 << 4);

		ecntl |= FEC_ECR_EN1588;



#ifndef CONFIG_M5272

	/* Enable the MIB statistic event counters */
@@ -1152,7 +1167,7 @@ static void 
fec_stop(struct net_device *ndev)

{

	struct fec_enet_private *fep = netdev_priv(ndev);

	u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);

	u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & FEC_RCR_RMII;

	u32 val;



	/* We cannot expect a graceful transmit stop without link !!! */
@@ -1171,7 +1186,7 @@ fec_stop(struct net_device *ndev) 
		if (fep->quirks & FEC_QUIRK_HAS_AVB) {

			writel(0, fep->hwp + FEC_ECNTRL);

		} else {

			writel(1, fep->hwp + FEC_ECNTRL);

			writel(FEC_ECR_RESET, fep->hwp + FEC_ECNTRL);

			udelay(10);

		}

		writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
@@ -1187,12 +1202,11 @@ fec_stop(struct net_device *ndev) 
	/* We have to keep ENET enabled to have MII interrupt stay working */

	if (fep->quirks & FEC_QUIRK_ENET_MAC &&

		!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {

		writel(2, fep->hwp + FEC_ECNTRL);

		writel(FEC_ECR_ETHEREN, fep->hwp + FEC_ECNTRL);

		writel(rmii_mode, fep->hwp + FEC_R_CNTRL);

	}

}





static void

fec_timeout(struct net_device *ndev)

{