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Commit c1cc28e6 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Make coresight optional 



Make coresight support conditional on a new Kconfig option. Support this
by moving the code around a bit and out of the generic headers to make
possible to omit the coresight code when the support isn't available.

This allows us to omit coresight when CONFIG_CORESIGHT isn't enabled
and optionally to remove it at the KGSL level too.

Change-Id: Ic0dedbad2a55df4acf1b8c6e15e5b1b39f08a832
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 7a6368ee

drivers/gpu/msm/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -13,3 +13,11 @@ config QCOM_ADRENO_DEFAULT_GOVERNOR 
	string "devfreq governor for the adreno core"

	default "simple_ondemand"

	depends on QCOM_KGSL



config QCOM_KGSL_CORESIGHT

	bool "Enable coresight support for the Adreno GPU"

	depends on QCOM_KGSL && CORESIGHT

	help

	  When enabled, the Adreno GPU is available as a source for Coresight

	  data. On a6xx targets there are two sources available for the GX and

	  CX domains respectively. Debug kernels should say 'Y' here.

drivers/gpu/msm/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,6 @@ msm_kgsl-y += \ 
	adreno_a6xx_preempt.o \

	adreno_a6xx_rgmu.o \

	adreno_a6xx_snapshot.o \

	adreno_coresight.o \

	adreno_cp_parser.o \

	adreno_dispatch.o \

	adreno_drawctxt.o \
@@ -49,5 +48,6 @@ msm_kgsl-y += \ 
	adreno_trace.o



msm_kgsl-$(CONFIG_COMPAT) += adreno_compat.o

msm_kgsl-$(CONFIG_QCOM_KGSL_CORESIGHT) += adreno_coresight.o

msm_kgsl-$(CONFIG_DEBUG_FS) += adreno_debugfs.o adreno_profile.o

msm_kgsl-$(CONFIG_ARM_SMMU) += adreno_iommu.o

drivers/gpu/msm/adreno.h

+3 −62
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ 
#ifndef __ADRENO_H

#define __ADRENO_H



#include "adreno_coresight.h"

#include "adreno_dispatch.h"

#include "adreno_drawctxt.h"

#include "adreno_perfcounter.h"
@@ -364,12 +365,6 @@ struct adreno_gpu_core { 
	u32 bus_width;

};



enum gpu_coresight_sources {

	GPU_CORESIGHT_GX = 0,

	GPU_CORESIGHT_CX = 1,

	GPU_CORESIGHT_MAX,

};



/**

 * struct adreno_device - The mothership structure for all adreno related info

 * @dev: Reference to struct kgsl_device
@@ -520,7 +515,7 @@ struct adreno_device { 
	unsigned int highest_bank_bit;

	unsigned int quirks;



	struct coresight_device *csdev[GPU_CORESIGHT_MAX];

	struct coresight_device *csdev[2];

	uint32_t gpmu_throttle_counters[ADRENO_GPMU_THROTTLE_COUNTERS];

	struct work_struct irq_storm_work;
@@ -733,53 +728,6 @@ struct adreno_vbif_snapshot_registers { 
	const int count;

};



/**

 * struct adreno_coresight_register - Definition for a coresight (tracebus)

 * debug register

 * @offset: Offset of the debug register in the KGSL mmio region

 * @initial: Default value to write when coresight is enabled

 * @value: Current shadow value of the register (to be reprogrammed after power

 * collapse)

 */

struct adreno_coresight_register {

	unsigned int offset;

	unsigned int initial;

	unsigned int value;

};



struct adreno_coresight_attr {

	struct device_attribute attr;

	struct adreno_coresight_register *reg;

};



ssize_t adreno_coresight_show_register(struct device *device,

		struct device_attribute *attr, char *buf);



ssize_t adreno_coresight_store_register(struct device *dev,

		struct device_attribute *attr, const char *buf, size_t size);



#define ADRENO_CORESIGHT_ATTR(_attrname, _reg) \

	struct adreno_coresight_attr coresight_attr_##_attrname  = { \

		__ATTR(_attrname, 0644, \

		adreno_coresight_show_register, \

		adreno_coresight_store_register), \

		(_reg), }



/**

 * struct adreno_coresight - GPU specific coresight definition

 * @registers - Array of GPU specific registers to configure trace bus output

 * @count - Number of registers in the array

 * @groups - Pointer to an attribute list of control files

 * @atid - The unique ATID value of the coresight device

 */

struct adreno_coresight {

	struct adreno_coresight_register *registers;

	unsigned int count;

	const struct attribute_group **groups;

	unsigned int atid;

};





struct adreno_irq_funcs {

	void (*func)(struct adreno_device *adreno_dev, int mask);

};
@@ -819,7 +767,7 @@ struct adreno_gpudev { 


	struct adreno_perfcounters *perfcounters;



	struct adreno_coresight *coresight[GPU_CORESIGHT_MAX];

	struct adreno_coresight *coresight[2];



	struct adreno_irq *irq;

	int num_prio_levels;
@@ -988,13 +936,6 @@ void adreno_fault_skipcmd_detached(struct adreno_device *adreno_dev, 
					 struct adreno_context *drawctxt,

					 struct kgsl_drawobj *drawobj);



void adreno_coresight_init(struct adreno_device *adreno_dev);



void adreno_coresight_start(struct adreno_device *adreno_dev);

void adreno_coresight_stop(struct adreno_device *adreno_dev);



void adreno_coresight_remove(struct adreno_device *adreno_dev);



bool adreno_hw_isidle(struct adreno_device *adreno_dev);



void adreno_fault_detect_start(struct adreno_device *adreno_dev);

drivers/gpu/msm/adreno_a3xx.c

+4 −0
Original line number Diff line number Diff line
@@ -1142,6 +1142,7 @@ static void a3xx_start(struct adreno_device *adreno_dev) 


}



#ifdef CONFIG_QCOM_KGSL_CORESIGHT

static struct adreno_coresight_register a3xx_coresight_registers[] = {

	{ A3XX_RBBM_DEBUG_BUS_CTL, 0x0001093F },

	{ A3XX_RBBM_EXT_TRACE_STOP_CNT, 0x00017fff },
@@ -1191,6 +1192,7 @@ static struct adreno_coresight a3xx_coresight = { 
	.count = ARRAY_SIZE(a3xx_coresight_registers),

	.groups = a3xx_coresight_groups,

};

#endif



static unsigned int a3xx_int_bits[ADRENO_INT_BITS_MAX] = {

	ADRENO_INT_DEFINE(ADRENO_INT_RBBM_AHB_ERROR, A3XX_INT_RBBM_AHB_ERROR),
@@ -1445,6 +1447,8 @@ struct adreno_gpudev adreno_a3xx_gpudev = { 
	.microcode_read = a3xx_microcode_read,

	.start = a3xx_start,

	.snapshot = a3xx_snapshot,

#ifdef CONFIG_QCOM_KGSL_CORESIGHT

	.coresight = {&a3xx_coresight},

#endif

	.clk_set_options = a3xx_clk_set_options,

};

drivers/gpu/msm/adreno_a5xx.c

+4 −0
Original line number Diff line number Diff line
@@ -2857,6 +2857,7 @@ static struct adreno_irq a5xx_irq = { 
	.mask = A5XX_INT_MASK,

};



#ifdef CONFIG_QCOM_KGSL_CORESIGHT

static struct adreno_coresight_register a5xx_coresight_registers[] = {

	{ A5XX_RBBM_CFG_DBGBUS_SEL_A },

	{ A5XX_RBBM_CFG_DBGBUS_SEL_B },
@@ -3049,13 +3050,16 @@ static struct adreno_coresight a5xx_coresight = { 
	.count = ARRAY_SIZE(a5xx_coresight_registers),

	.groups = a5xx_coresight_groups,

};

#endif



struct adreno_gpudev adreno_a5xx_gpudev = {

	.reg_offsets = a5xx_register_offsets,

	.int_bits = a5xx_int_bits,

	.ft_perf_counters = a5xx_ft_perf_counters,

	.ft_perf_counters_count = ARRAY_SIZE(a5xx_ft_perf_counters),

#ifdef CONFIG_QCOM_KGSL_CORESIGHT

	.coresight = {&a5xx_coresight},

#endif

	.start = a5xx_start,

	.snapshot = a5xx_snapshot,

	.irq = &a5xx_irq,