Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c1866d44 authored by Abhinav Kumar's avatar Abhinav Kumar Committed by Rob Clark
Browse files

drm/msm/dsi: fix dsi clock names in DSI 10nm PLL driver 



Fix the dsi clock names in the DSI 10nm PLL driver to
match the names in the dispcc driver as those are
according to the clock plan of the chipset.

Changes in v2:
- Update the clock diagram with the new clock name

Reviewed-by: default avatarSean Paul <seanpaul@chromium.org>
Signed-off-by: default avatarAbhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: default avatarSean Paul <seanpaul@chromium.org>
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent b2ccfdf1

drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c

+4 −4
Original line number Original line Diff line number Diff line
@@ -17,7 +17,7 @@ 
 *                              |                |

 *                              |                |

 *                              |                |

 *                              |                |

 *                 +---------+  |  +----------+  |  +----+

 *                 +---------+  |  +----------+  |  +----+

 *  dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0pllbyte

 *  dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk

 *                 +---------+  |  +----------+  |  +----+

 *                 +---------+  |  +----------+  |  +----+

 *                              |                |

 *                              |                |

 *                              |                |         dsi0_pll_by_2_bit_clk

 *                              |                |         dsi0_pll_by_2_bit_clk
@@ -25,7 +25,7 @@ 
 *                              |                |  +----+  |  |\  dsi0_pclk_mux

 *                              |                |  +----+  |  |\  dsi0_pclk_mux

 *                              |                |--| /2 |--o--| \   |

 *                              |                |--| /2 |--o--| \   |

 *                              |                |  +----+     |  \  |  +---------+

 *                              |                |  +----+     |  \  |  +---------+

 *                              |                --------------|  |--o--| div_7_4 |-- dsi0pll

 *                              |                --------------|  |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk

 *                              |------------------------------|  /     +---------+

 *                              |------------------------------|  /     +---------+

 *                              |          +-----+             | /

 *                              |          +-----+             | /

 *                              -----------| /4? |--o----------|/

 *                              -----------| /4? |--o----------|/
@@ -688,7 +688,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm) 




	hws[num++] = hw;

	hws[num++] = hw;





	snprintf(clk_name, 32, "dsi%dpllbyte", pll_10nm->id);

	snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id);

	snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);

	snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);





	/* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */

	/* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
@@ -737,7 +737,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm) 




	hws[num++] = hw;

	hws[num++] = hw;





	snprintf(clk_name, 32, "dsi%dpll", pll_10nm->id);

	snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id);

	snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id);

	snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id);





	/* PIX CLK DIV : DIV_CTRL_7_4*/

	/* PIX CLK DIV : DIV_CTRL_7_4*/