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Commit c13bbf4a authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.20' of git://people.freedesktop.org/~agd5f/linux into drm-next 



Fixes for 4.20.  Highlights:
- VCN DPG fixes for Picasso
- Add support for the latest vega20 vbios
- Scheduler timeout fix
- License fixes for radeon and amdgpu
- Misc other fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181017215427.2804-1-alexander.deucher@amd.com
parents 28b32b9f 8e16695b

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

+2 −10
Original line number Diff line number Diff line
@@ -826,21 +826,13 @@ int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) 
{

	struct drm_minor *minor = adev->ddev->primary;

	struct dentry *ent, *root = minor->debugfs_root;

	unsigned i, j;

	unsigned int i;



	for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {

		ent = debugfs_create_file(debugfs_regs_names[i],

					  S_IFREG | S_IRUGO, root,

					  adev, debugfs_regs[i]);

		if (IS_ERR(ent)) {

			for (j = 0; j < i; j++) {

				debugfs_remove(adev->debugfs_regs[i]);

				adev->debugfs_regs[i] = NULL;

			}

			return PTR_ERR(ent);

		}



		if (!i)

		if (!i && !IS_ERR_OR_NULL(ent))

			i_size_write(ent->d_inode, adev->rmmio_size);

		adev->debugfs_regs[i] = ent;

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c

+1 −1
Original line number Diff line number Diff line
@@ -574,7 +574,7 @@ void amdgpu_vmid_mgr_init(struct amdgpu_device *adev) 
		/* skip over VMID 0, since it is the system VM */

		for (j = 1; j < id_mgr->num_ids; ++j) {

			amdgpu_vmid_reset(adev, i, j);

			amdgpu_sync_create(&id_mgr->ids[i].active);

			amdgpu_sync_create(&id_mgr->ids[j].active);

			list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);

		}

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c

+1 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

// SPDX-License-Identifier: MIT

/* Copyright Red Hat Inc 2010.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+15 −1
Original line number Diff line number Diff line
@@ -97,6 +97,7 @@ MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); 
static const struct soc15_reg_golden golden_settings_gc_9_0[] =

{

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
@@ -4904,7 +4905,20 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) 
static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)

{

	/* init asci gds info */

	adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);

	switch (adev->asic_type) {

	case CHIP_VEGA10:

	case CHIP_VEGA12:

	case CHIP_VEGA20:

		adev->gds.mem.total_size = 0x10000;

		break;

	case CHIP_RAVEN:

		adev->gds.mem.total_size = 0x1000;

		break;

	default:

		adev->gds.mem.total_size = 0x10000;

		break;

	}



	adev->gds.gws.total_size = 64;

	adev->gds.oa.total_size = 16;

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

+2 −0
Original line number Diff line number Diff line
@@ -148,6 +148,7 @@ static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 
	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xFE000000, 0x00000000),

};



static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
@@ -177,6 +178,7 @@ static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 
	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xFE000000, 0x00000000),

};



static const struct soc15_reg_golden golden_settings_sdma_rv1[] =