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Commit c129b6fe authored by Anson Huang's avatar Anson Huang Committed by Shawn Guo
Browse files

clk: imx: Use imx_mmdc_mask_handshake() API for masking MMDC channel 



Use imx_mmdc_mask_handshake() API instead of programming CCM
register directly in each platform to mask unused MMDC channel's
handshake.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Reviewed-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent efdb2790

drivers/clk/imx/clk-imx6q.c

+1 −12
Original line number Diff line number Diff line
@@ -260,25 +260,14 @@ static bool pll6_bypassed(struct device_node *node) 
	return false;

}



#define CCM_CCDR		0x04

#define CCM_CCSR		0x0c

#define CCM_CS2CDR		0x2c



#define CCDR_MMDC_CH1_MASK		BIT(16)

#define CCSR_PLL3_SW_CLK_SEL		BIT(0)



#define CS2CDR_LDB_DI0_CLK_SEL_SHIFT	9

#define CS2CDR_LDB_DI1_CLK_SEL_SHIFT	12



static void __init imx6q_mmdc_ch1_mask_handshake(void __iomem *ccm_base)

{

	unsigned int reg;



	reg = readl_relaxed(ccm_base + CCM_CCDR);

	reg |= CCDR_MMDC_CH1_MASK;

	writel_relaxed(reg, ccm_base + CCM_CCDR);

}



/*

 * The only way to disable the MMDC_CH1 clock is to move it to pll3_sw_clk

 * via periph2_clk2_sel and then to disable pll3_sw_clk by selecting the
@@ -651,7 +640,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 


	disable_anatop_clocks(anatop_base);



	imx6q_mmdc_ch1_mask_handshake(base);

	imx_mmdc_mask_handshake(base, 1);



	if (clk_on_imx6qp()) {

		clk[IMX6QDL_CLK_LDB_DI0_SEL]      = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9,  3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);

drivers/clk/imx/clk-imx6sl.c

+1 −4
Original line number Diff line number Diff line
@@ -17,8 +17,6 @@ 


#include "clk.h"



#define CCDR				0x4

#define BM_CCM_CCDR_MMDC_CH0_MASK	(1 << 17)

#define CCSR			0xc

#define BM_CCSR_PLL1_SW_CLK_SEL	(1 << 2)

#define CACRR			0x10
@@ -414,8 +412,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) 
	clks[IMX6SL_CLK_USDHC4]       = imx_clk_gate2("usdhc4",       "usdhc4_podf",       base + 0x80, 8);



	/* Ensure the MMDC CH0 handshake is bypassed */

	writel_relaxed(readl_relaxed(base + CCDR) |

		BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);

	imx_mmdc_mask_handshake(base, 0);



	imx_check_clocks(clks, ARRAY_SIZE(clks));

drivers/clk/imx/clk-imx6sll.c

+1 −2
Original line number Diff line number Diff line
@@ -16,7 +16,6 @@ 
#include "clk.h"



#define CCM_ANALOG_PLL_BYPASS		(0x1 << 16)

#define BM_CCM_CCDR_MMDC_CH0_MASK	(0x2 << 16)

#define xPLL_CLR(offset)		(offset + 0x8)



static const char *pll_bypass_src_sels[] = { "osc", "dummy", };
@@ -340,7 +339,7 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node) 
	clks[IMX6SLL_CLK_USDHC3]	= imx_clk_gate2("usdhc3", "usdhc3_podf",  base + 0x80,	6);



	/* mask handshake of mmdc */

	writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + 0x4);

	imx_mmdc_mask_handshake(base, 0);



	imx_check_clocks(clks, ARRAY_SIZE(clks));

drivers/clk/imx/clk-imx6sx.c

+1 −4
Original line number Diff line number Diff line
@@ -22,9 +22,6 @@ 


#include "clk.h"



#define CCDR    0x4

#define BM_CCM_CCDR_MMDC_CH0_MASK       (0x2 << 16)



static const char *step_sels[]		= { "osc", "pll2_pfd2_396m", };

static const char *pll1_sw_sels[]	= { "pll1_sys", "step", };

static const char *periph_pre_sels[]	= { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
@@ -488,7 +485,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) 
	clks[IMX6SX_CLK_CKO2]         = imx_clk_gate("cko2",           "cko2_podf",         base + 0x60, 24);



	/* mask handshake of mmdc */

	writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);

	imx_mmdc_mask_handshake(base, 0);



	imx_check_clocks(clks, ARRAY_SIZE(clks));

drivers/clk/imx/clk-imx6ul.c

+1 −4
Original line number Diff line number Diff line
@@ -22,9 +22,6 @@ 


#include "clk.h"



#define BM_CCM_CCDR_MMDC_CH0_MASK	(0x2 << 16)

#define CCDR	0x4



static const char *pll_bypass_src_sels[] = { "osc", "dummy", };

static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };

static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
@@ -464,7 +461,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 
	clks[IMX6UL_CLK_CKO2]		= imx_clk_gate("cko2",		"cko2_podf",	 base + 0x60,	24);



	/* mask handshake of mmdc */

	writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);

	imx_mmdc_mask_handshake(base, 0);



	imx_check_clocks(clks, ARRAY_SIZE(clks));