Merge "clk: qcom: clk-dummy: Add a dummy clock provider" (c126bd57) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/clk/qcom/Makefile

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		@@ -14,6 +14,7 @@ clk-qcom-y += clk-regmap-mux-div.o
		clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
		clk-qcom-y += clk-hfpll.o
		clk-qcom-y += reset.o
		clk-qcom-y += clk-dummy.o
		clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o

		# Keep alphabetically sorted by config

drivers/clk/qcom/clk-dummy.c

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		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
		*/

		#include <linux/clk-provider.h>
		#include <linux/of.h>
		#include <linux/platform_device.h>
		#include <linux/slab.h>

		#include "common.h"

		#define to_clk_dummy(_hw) container_of(_hw, struct clk_dummy, hw)

		#define RESET_MAX 100

		static int dummy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
		{
		struct clk_dummy *dummy = to_clk_dummy(hw);

		dummy->rrate = rate;

		pr_debug("%s: rate %lu\n", __func__, rate);

		return 0;
		}

		static long dummy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long *parent_rate)
		{
		return rate;
		}

		static unsigned long dummy_clk_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
		{
		struct clk_dummy *dummy = to_clk_dummy(hw);

		pr_debug("%s: returning a clock rate of %lu\n",
		__func__, dummy->rrate);

		return dummy->rrate;
		}

		const struct clk_ops clk_dummy_ops = {
		.set_rate = dummy_clk_set_rate,
		.round_rate = dummy_clk_round_rate,
		.recalc_rate = dummy_clk_recalc_rate,
		};
		EXPORT_SYMBOL(clk_dummy_ops);

		static int dummy_reset_assert(struct reset_controller_dev *rcdev,
		unsigned long id)
		{
		return 0;
		}

		static int dummy_reset_deassert(struct reset_controller_dev *rcdev,
		unsigned long id)
		{
		return 0;
		}

		static struct reset_control_ops dummy_reset_ops = {
		.assert = dummy_reset_assert,
		.deassert = dummy_reset_deassert,
		};

		/**
		* clk_register_dummy - register dummy clock with the
		* clock framework
		* @dev: device that is registering this clock
		* @name: name of this clock
		* @flags: framework-specific flags
		* @node: device node
		*/
		static struct clk clk_register_dummy(struct device dev, const char *name,
		unsigned long flags, struct device_node *node)
		{
		struct clk_dummy *dummy;
		struct clk *clk;
		struct clk_init_data init = {};

		/* allocate dummy clock */
		dummy = kzalloc(sizeof(*dummy), GFP_KERNEL);
		if (!dummy)
		return ERR_PTR(-ENOMEM);

		init.name = name;
		init.ops = &clk_dummy_ops;
		init.flags = flags;
		init.num_parents = 0;
		dummy->hw.init = &init;

		/* register the clock */
		clk = clk_register(dev, &dummy->hw);
		if (IS_ERR(clk)) {
		kfree(dummy);
		return clk;
		}

		dummy->reset.of_node = node;
		dummy->reset.ops = &dummy_reset_ops;
		dummy->reset.nr_resets = RESET_MAX;

		if (reset_controller_register(&dummy->reset))
		pr_err("Failed to register reset controller for %s\n", name);
		else
		pr_info("Successfully registered dummy reset controller for %s\n",
		name);

		return clk;
		}

		/**
		* of_dummy_clk_setup() - Setup function for simple fixed rate clock
		*/
		static void of_dummy_clk_setup(struct device_node *node)
		{
		struct clk *clk;
		const char *clk_name = "dummy_clk";

		of_property_read_string(node, "clock-output-names", &clk_name);

		clk = clk_register_dummy(NULL, clk_name, 0, node);
		if (!IS_ERR(clk)) {
		of_clk_add_provider(node, of_clk_src_simple_get, clk);
		} else {
		pr_err("Failed to register dummy clock controller for %s\n",
		clk_name);
		return;
		}

		pr_info("Successfully registered dummy clock controller for %s\n",
		clk_name);
		}
		CLK_OF_DECLARE(dummy_clk, "qcom,dummycc", of_dummy_clk_setup);

drivers/clk/qcom/common.h

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		/* SPDX-License-Identifier: GPL-2.0 */
		/* Copyright (c) 2014, The Linux Foundation. All rights reserved. */
		/* SPDX-License-Identifier: GPL-2.0-only */
		/* Copyright (c) 2014, 2018, The Linux Foundation. All rights reserved. */

		#ifndef __QCOM_CLK_COMMON_H__
		#define __QCOM_CLK_COMMON_H__

		#include <linux/reset-controller.h>

		struct platform_device;
		struct regmap_config;
		struct clk_regmap;
		@@ -41,6 +43,12 @@ struct parent_map {
		u8 cfg;
		};

		struct clk_dummy {
		struct clk_hw hw;
		struct reset_controller_dev reset;
		unsigned long rrate;
		};

		extern const struct freq_tbl qcom_find_freq(const struct freq_tbl f,
		unsigned long rate);
		extern const struct freq_tbl qcom_find_freq_floor(const struct freq_tbl f,
		@@ -61,5 +69,5 @@ extern int qcom_cc_really_probe(struct platform_device *pdev,
		struct regmap *regmap);
		extern int qcom_cc_probe(struct platform_device *pdev,
		const struct qcom_cc_desc *desc);

		extern const struct clk_ops clk_dummy_ops;
		#endif

include/dt-bindings/clock/qcom,aop-qmp.h

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		/* SPDX-License-Identifier: GPL-2.0-only */
		/* Copyright (c) 2019, The Linux Foundation. All rights reserved. */

		#ifndef _DT_BINDINGS_CLK_QCOM_AOP_QMP_H
		#define _DT_BINDINGS_CLK_QCOM_AOP_QMP_H

		#define QDSS_CLK_LEVEL_OFF 0
		#define QDSS_CLK_LEVEL_DYNAMIC 1
		#define QDSS_CLK_LEVEL_TURBO 2
		#define QDSS_CLK_LEVEL_NOMINAL 3
		#define QDSS_CLK_LEVEL_SVS_L1 4
		#define QDSS_CLK_LEVEL_SVS 5
		#define QDSS_CLK_LEVEL_LOW_SVS 6
		#define QDSS_CLK_LEVEL_MIN_SVS 7

		/* clocks id */
		#define QDSS_CLK 0
		#define QDSS_AO_CLK 1
		#endif

include/dt-bindings/clock/qcom,camcc-lahaina.h

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		/* SPDX-License-Identifier: GPL-2.0-only */
		/*
		* Copyright (c) 2019, The Linux Foundation. All rights reserved.
		*/

		#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_LAHAINA_H
		#define _DT_BINDINGS_CLK_QCOM_CAM_CC_LAHAINA_H

		/* CAM_CC clocks */
		#define CAM_CC_BPS_AHB_CLK 0
		#define CAM_CC_BPS_AREG_CLK 1
		#define CAM_CC_BPS_AXI_CLK 2
		#define CAM_CC_BPS_CLK 3
		#define CAM_CC_BPS_CLK_SRC 4
		#define CAM_CC_CAMNOC_AXI_CLK 5
		#define CAM_CC_CAMNOC_AXI_CLK_SRC 6
		#define CAM_CC_CAMNOC_DCD_XO_CLK 7
		#define CAM_CC_CCI_0_CLK 8
		#define CAM_CC_CCI_0_CLK_SRC 9
		#define CAM_CC_CCI_1_CLK 10
		#define CAM_CC_CCI_1_CLK_SRC 11
		#define CAM_CC_CORE_AHB_CLK 12
		#define CAM_CC_CPAS_AHB_CLK 13
		#define CAM_CC_CPHY_RX_CLK_SRC 14
		#define CAM_CC_CSI0PHYTIMER_CLK 15
		#define CAM_CC_CSI0PHYTIMER_CLK_SRC 16
		#define CAM_CC_CSI1PHYTIMER_CLK 17
		#define CAM_CC_CSI1PHYTIMER_CLK_SRC 18
		#define CAM_CC_CSI2PHYTIMER_CLK 19
		#define CAM_CC_CSI2PHYTIMER_CLK_SRC 20
		#define CAM_CC_CSI3PHYTIMER_CLK 21
		#define CAM_CC_CSI3PHYTIMER_CLK_SRC 22
		#define CAM_CC_CSI4PHYTIMER_CLK 23
		#define CAM_CC_CSI4PHYTIMER_CLK_SRC 24
		#define CAM_CC_CSI5PHYTIMER_CLK 25
		#define CAM_CC_CSI5PHYTIMER_CLK_SRC 26
		#define CAM_CC_CSIPHY0_CLK 27
		#define CAM_CC_CSIPHY1_CLK 28
		#define CAM_CC_CSIPHY2_CLK 29
		#define CAM_CC_CSIPHY3_CLK 30
		#define CAM_CC_CSIPHY4_CLK 31
		#define CAM_CC_CSIPHY5_CLK 32
		#define CAM_CC_FAST_AHB_CLK_SRC 33
		#define CAM_CC_GDSC_CLK 34
		#define CAM_CC_ICP_AHB_CLK 35
		#define CAM_CC_ICP_CLK 36
		#define CAM_CC_ICP_CLK_SRC 37
		#define CAM_CC_IFE_0_AHB_CLK 38
		#define CAM_CC_IFE_0_AREG_CLK 39
		#define CAM_CC_IFE_0_AXI_CLK 40
		#define CAM_CC_IFE_0_CLK 41
		#define CAM_CC_IFE_0_CLK_SRC 42
		#define CAM_CC_IFE_0_CPHY_RX_CLK 43
		#define CAM_CC_IFE_0_CSID_CLK 44
		#define CAM_CC_IFE_0_CSID_CLK_SRC 45
		#define CAM_CC_IFE_0_DSP_CLK 46
		#define CAM_CC_IFE_1_AHB_CLK 47
		#define CAM_CC_IFE_1_AREG_CLK 48
		#define CAM_CC_IFE_1_AXI_CLK 49
		#define CAM_CC_IFE_1_CLK 50
		#define CAM_CC_IFE_1_CLK_SRC 51
		#define CAM_CC_IFE_1_CPHY_RX_CLK 52
		#define CAM_CC_IFE_1_CSID_CLK 53
		#define CAM_CC_IFE_1_CSID_CLK_SRC 54
		#define CAM_CC_IFE_1_DSP_CLK 55
		#define CAM_CC_IFE_2_AHB_CLK 56
		#define CAM_CC_IFE_2_AREG_CLK 57
		#define CAM_CC_IFE_2_AXI_CLK 58
		#define CAM_CC_IFE_2_CLK 59
		#define CAM_CC_IFE_2_CLK_SRC 60
		#define CAM_CC_IFE_2_CPHY_RX_CLK 61
		#define CAM_CC_IFE_2_CSID_CLK 62
		#define CAM_CC_IFE_2_CSID_CLK_SRC 63
		#define CAM_CC_IFE_LITE_AHB_CLK 64
		#define CAM_CC_IFE_LITE_AXI_CLK 65
		#define CAM_CC_IFE_LITE_CLK 66
		#define CAM_CC_IFE_LITE_CLK_SRC 67
		#define CAM_CC_IFE_LITE_CPHY_RX_CLK 68
		#define CAM_CC_IFE_LITE_CSID_CLK 69
		#define CAM_CC_IFE_LITE_CSID_CLK_SRC 70
		#define CAM_CC_IPE_0_AHB_CLK 71
		#define CAM_CC_IPE_0_AREG_CLK 72
		#define CAM_CC_IPE_0_AXI_CLK 73
		#define CAM_CC_IPE_0_CLK 74
		#define CAM_CC_IPE_0_CLK_SRC 75
		#define CAM_CC_JPEG_CLK 76
		#define CAM_CC_JPEG_CLK_SRC 77
		#define CAM_CC_MCLK0_CLK 78
		#define CAM_CC_MCLK0_CLK_SRC 79
		#define CAM_CC_MCLK1_CLK 80
		#define CAM_CC_MCLK1_CLK_SRC 81
		#define CAM_CC_MCLK2_CLK 82
		#define CAM_CC_MCLK2_CLK_SRC 83
		#define CAM_CC_MCLK3_CLK 84
		#define CAM_CC_MCLK3_CLK_SRC 85
		#define CAM_CC_MCLK4_CLK 86
		#define CAM_CC_MCLK4_CLK_SRC 87
		#define CAM_CC_MCLK5_CLK 88
		#define CAM_CC_MCLK5_CLK_SRC 89
		#define CAM_CC_PLL0 90
		#define CAM_CC_PLL0_OUT_EVEN 91
		#define CAM_CC_PLL0_OUT_ODD 92
		#define CAM_CC_PLL1 93
		#define CAM_CC_PLL1_OUT_EVEN 94
		#define CAM_CC_PLL2 95
		#define CAM_CC_PLL3 96
		#define CAM_CC_PLL3_OUT_EVEN 97
		#define CAM_CC_PLL4 98
		#define CAM_CC_PLL4_OUT_EVEN 99
		#define CAM_CC_PLL5 100
		#define CAM_CC_PLL5_OUT_EVEN 101
		#define CAM_CC_PLL6 102
		#define CAM_CC_PLL6_OUT_EVEN 103
		#define CAM_CC_SBI_AHB_CLK 104
		#define CAM_CC_SBI_AXI_CLK 105
		#define CAM_CC_SBI_CLK 106
		#define CAM_CC_SBI_CPHY_RX_0_CLK 107
		#define CAM_CC_SBI_CPHY_RX_1_CLK 108
		#define CAM_CC_SBI_CSID_0_CLK 109
		#define CAM_CC_SBI_CSID_1_CLK 110
		#define CAM_CC_SBI_CSID_CLK_SRC 111
		#define CAM_CC_SBI_DIV_CLK_SRC 112
		#define CAM_CC_SBI_IFE_0_CLK 113
		#define CAM_CC_SBI_IFE_1_CLK 114
		#define CAM_CC_SBI_IFE_2_CLK 115
		#define CAM_CC_SLEEP_CLK 116
		#define CAM_CC_SLEEP_CLK_SRC 117
		#define CAM_CC_SLOW_AHB_CLK_SRC 118
		#define CAM_CC_XO_CLK_SRC 119

		/* CAM_CC resets */
		#define CAM_CC_BPS_BCR 0
		#define CAM_CC_ICP_BCR 1
		#define CAM_CC_IFE_0_BCR 2
		#define CAM_CC_IFE_1_BCR 3
		#define CAM_CC_IFE_2_BCR 4
		#define CAM_CC_IPE_0_BCR 5
		#define CAM_CC_SBI_BCR 6

		#endif