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Commit c11b813f authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: s/PUNIT_REG_DSPFREQ/PUNIT_REG_DSPSSPM/ 



Rename the punit display power register to match the spec.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181129175504.3630-1-ville.syrjala@linux.intel.com


Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
parent 62eb3c24

drivers/gpu/drm/i915/i915_reg.h

+1 −1
Original line number Diff line number Diff line
@@ -1044,7 +1044,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
/* See configdb bunit SB addr map */

#define BUNIT_REG_BISOC				0x11



#define PUNIT_REG_DSPFREQ			0x36

#define PUNIT_REG_DSPSSPM			0x36

#define   DSPFREQSTAT_SHIFT_CHV			24

#define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)

#define   DSPFREQGUAR_SHIFT_CHV			8

drivers/gpu/drm/i915/intel_cdclk.c

+7 −7
Original line number Diff line number Diff line
@@ -468,7 +468,7 @@ static void vlv_get_cdclk(struct drm_i915_private *dev_priv, 
					       cdclk_state->vco);



	mutex_lock(&dev_priv->pcu_lock);

	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);

	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);

	mutex_unlock(&dev_priv->pcu_lock);



	if (IS_VALLEYVIEW(dev_priv))
@@ -543,11 +543,11 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, 
	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);



	mutex_lock(&dev_priv->pcu_lock);

	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);

	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);

	val &= ~DSPFREQGUAR_MASK;

	val |= (cmd << DSPFREQGUAR_SHIFT);

	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);

	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &

	vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);

	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &

		      DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),

		     50)) {

		DRM_ERROR("timed out waiting for CDclk change\n");
@@ -624,11 +624,11 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv, 
	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);



	mutex_lock(&dev_priv->pcu_lock);

	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);

	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);

	val &= ~DSPFREQGUAR_MASK_CHV;

	val |= (cmd << DSPFREQGUAR_SHIFT_CHV);

	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);

	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &

	vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);

	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &

		      DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),

		     50)) {

		DRM_ERROR("timed out waiting for CDclk change\n");

drivers/gpu/drm/i915/intel_pm.c

+3 −3
Original line number Diff line number Diff line
@@ -335,12 +335,12 @@ static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) 


	mutex_lock(&dev_priv->pcu_lock);



	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);

	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);

	if (enable)

		val |= DSP_MAXFIFO_PM5_ENABLE;

	else

		val &= ~DSP_MAXFIFO_PM5_ENABLE;

	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);

	vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);



	mutex_unlock(&dev_priv->pcu_lock);

}
@@ -6063,7 +6063,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv) 
	if (IS_CHERRYVIEW(dev_priv)) {

		mutex_lock(&dev_priv->pcu_lock);



		val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);

		val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);

		if (val & DSP_MAXFIFO_PM5_ENABLE)

			wm->level = VLV_WM_LEVEL_PM5;

drivers/gpu/drm/i915/intel_runtime_pm.c

+6 −6
Original line number Diff line number Diff line
@@ -1760,7 +1760,7 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 


	mutex_lock(&dev_priv->pcu_lock);



	state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);

	state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);

	/*

	 * We only ever set the power-on and power-gate states, anything

	 * else is unexpected.
@@ -1772,7 +1772,7 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 
	 * A transient state at this point would mean some unexpected party

	 * is poking at the power controls too.

	 */

	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);

	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);

	WARN_ON(ctrl << 16 != state);



	mutex_unlock(&dev_priv->pcu_lock);
@@ -1793,20 +1793,20 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 
	mutex_lock(&dev_priv->pcu_lock);



#define COND \

	((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)

	((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state)



	if (COND)

		goto out;



	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);

	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);

	ctrl &= ~DP_SSC_MASK(pipe);

	ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);

	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);

	vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl);



	if (wait_for(COND, 100))

		DRM_ERROR("timeout setting power well state %08x (%08x)\n",

			  state,

			  vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));

			  vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM));



#undef COND