Commit c0a636e4 authored Dec 17, 2018 by Dinh Nguyen Committed by Stephen Boyd Jan 11, 2019

clk: socfpga: stratix10: fix rate calculation for pll clocks



The main PLL calculation has a mistake. We should be using the
multiplying the VCO frequency, not the parent clock frequency.

Fixes: 07afb8db ("clk: socfpga: stratix10: add clock driver for
Stratix10 platform")
Cc: linux-stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

parent 83b4c147

drivers/clk/socfpga/clk-pll-s10.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -43,7 +43,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
		/* Read mdiv and fdiv from the fdbck register */
		reg = readl(socfpgaclk->hw.reg + 0x4);
		mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT;
		vco_freq = (unsigned long long)parent_rate * (mdiv + 6);
		vco_freq = (unsigned long long)vco_freq * (mdiv + 6);

		return (unsigned long)vco_freq;
		}