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Commit c08691b5 authored by Wolfram Sang's avatar Wolfram Sang Committed by Simon Horman
Browse files

ARM: shmobile: r8a7791: add IIC(B) clocks to dtsi 



Signed-off-by: default avatarWolfram Sang <wsa@sang-engineering.com>
Acked-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: default avatarMagnus Damm <damm@opensource.se>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent c6e8f325

arch/arm/boot/dts/r8a7791.dtsi

+13 −12
Original line number Diff line number Diff line
@@ -716,15 +716,16 @@ 
		mstp3_clks: mstp3_clks@e615013c {

			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;

			clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>,

				<&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>;

			clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,

				 <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>;

			#clock-cells = <1>;

			renesas,clock-indices = <

				R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1

				R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1

				R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0

				R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_CMT1

			>;

			clock-output-names =

				"tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1";

				"tpu0", "sdhi2", "sdhi1", "sdhi0",

				"mmcif0", "i2c7", "i2c8", "cmt1";

		};

		mstp5_clks: mstp5_clks@e6150144 {

			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -768,17 +769,17 @@ 
		mstp9_clks: mstp9_clks@e6150994 {

			compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;

			clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>,

				 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,

				 <&p_clk>;

			clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&p_clk>,

				 <&cp_clk>, <&p_clk>, <&p_clk>, <&p_clk>,

				 <&p_clk>, <&p_clk>;

			#clock-cells = <1>;

			renesas,clock-indices = <

				R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD

				R8A7791_CLK_I2C5 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3

				R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0

				R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5

				R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2

				R8A7791_CLK_I2C1 R8A7791_CLK_I2C0

			>;

			clock-output-names =

				"rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3",

				"rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3",

				"i2c2", "i2c1", "i2c0";

		};

		mstp11_clks: mstp11_clks@e615099c {