Merge "ARM: dts: msm: add initial devicetree nodes for PCIe RC on sdxlemur" (c0553c87) · Commits · e / devices / android_kernel_fairphone_FP5

qcom/sdxlemur-pcie.dtsi

0 → 100644

+117 −0

Original line number	Original line	Diff line number	Diff line
			&soc {
			pcie0: qcom,pcie@1c00000 {
			compatible = "qcom,pci-msm";

			reg = <0x1c00000 0x3000>,
			<0x1c06000 0x2000>,
			<0x40000000 0xf1d>,
			<0x40000f20 0xa8>,
			<0x40001000 0x1000>,
			<0x40100000 0x100000>;
			reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";

			cell-index = <0>;
			linux,pci-domain = <0>;

			#address-cells = <3>;
			#size-cells = <2>;
			ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
			<0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>;

			interrupt-parent = <&pcie0>;
			interrupts = <0 1 2 3 4>;
			interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
			"int_d";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0xffffffff>;
			interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
			0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH
			0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH
			0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
			0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;

			msi-parent = <&pcie0_msi>;

			perst-gpio = <&tlmm 57 0>;
			wake-gpio = <&tlmm 53 0>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&pcie0_clkreq_default
			&pcie0_perst_default
			&pcie0_wake_default>;
			pinctrl-1 = <&pcie0_clkreq_sleep
			&pcie0_perst_default
			&pcie0_wake_default>;

			gdsc-vdd-supply = <&gcc_pcie_gdsc>;
			vreg-1.8-supply = <&pmx65_l1>;
			vreg-0.9-supply = <&pmx65_l4>;
			vreg-cx-supply = <&VDD_CX_LEVEL>;
			qcom,vreg-1.8-voltage-level = <1200000 1200000 30000>;
			qcom,vreg-0.9-voltage-level = <912000 912000 132000>;
			qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
			RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
			qcom,bw-scale =
			<RPMH_REGULATOR_LEVEL_LOW_SVS 100000000 /* Gen1 */
			RPMH_REGULATOR_LEVEL_LOW_SVS 100000000 /* Gen2 */
			RPMH_REGULATOR_LEVEL_LOW_SVS 100000000 /* Gen3 */
			RPMH_REGULATOR_LEVEL_LOW_SVS 100000000>; /* Gen4 */

			interconnect-names = "icc_path";
			interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;

			clocks = <&gcc GCC_PCIE_PIPE_CLK>,
			<&rpmhcc RPMH_CXO_CLK>,
			<&gcc GCC_PCIE_AUX_CLK>,
			<&gcc GCC_PCIE_CFG_AHB_CLK>,
			<&gcc GCC_PCIE_MSTR_AXI_CLK>,
			<&gcc GCC_PCIE_SLV_AXI_CLK>,
			<&gcc GCC_PCIE_0_CLKREF_EN>,
			<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
			<&gcc GCC_PCIE_SLEEP_CLK>,
			<&gcc GCC_PCIE_RCHNG_PHY_CLK>,
			<&gcc GCC_PCIE_PIPE_CLK_SRC>,
			<&gcc PCIE_PIPE_CLK>;

			clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
			"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
			"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
			"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
			"pcie_0_sleep_clk", "pcie_phy_refgen_clk",
			"pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src";
			max-clock-frequency-hz = <0>, <0>, <0>, <0>, <0>, <0>,
			<0>, <0>, <0>, <0>, <100000000>, <0>,
			<0>;

			resets = <&gcc GCC_PCIE_BCR>,
			<&gcc GCC_PCIE_PHY_BCR>;
			reset-names = "pcie_0_core_reset",
			"pcie_0_phy_reset";

			qcom,smmu-sid-base = <0x0200>;
			iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
			<0x100 &apps_smmu 0x0201 0x1>;

			qcom,boot-option = <0x1>;
			qcom,use-19p2mhz-aux-clk;
			qcom,slv-addr-space-size = <0x40000000>;
			qcom,ep-latency = <10>;

			qcom,pcie-phy-ver = <0>;
			qcom,phy-status-offset = <0x1214>;
			qcom,phy-status-bit = <7>;
			qcom,phy-power-down-offset = <0x1240>;

			pcie0_rp: pcie0_rp {
			reg = <0 0 0 0 0>;
			};
			};

			pcie0_msi: qcom,pcie0_msi@a0000000 {
			compatible = "qcom,pci-msi";
			msi-controller;
			reg = <0xa0000000 0x0>;
			interrupt-parent = <&intc>;
			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
			qcom,snps;
			};
			};

qcom/sdxlemur-pinctrl.dtsi

+54 −0

Original line number	Original line	Diff line number	Diff line
	@@ -39,5 +39,59 @@
	bias-disable;		bias-disable;
	};		};
	};		};

			pcie0 {
			pcie0_clkreq_default: pcie0_clkreq_default {
			mux {
			pins = "gpio56";
			function = "pcie_clkreq";
			};

			config {
			pins = "gpio56";
			drive-strength = <2>;
			bias-pull-up;
			};
			};

			pcie0_perst_default: pcie0_perst_default {
			mux {
			pins = "gpio57";
			function = "gpio";
			};

			config {
			pins = "gpio57";
			drive-strength = <2>;
			bias-pull-down;
			};
			};

			pcie0_wake_default: pcie0_wake_default {
			mux {
			pins = "gpio53";
			function = "gpio";
			};

			config {
			pins = "gpio53";
			drive-strength = <2>;
			bias-pull-up;
			};
			};

			pcie0_clkreq_sleep: pcie0_clkreq_sleep {
			mux {
			pins = "gpio56";
			function = "gpio";
			};

			config {
			pins = "gpio56";
			drive-strength = <2>;
			bias-pull-up;
			};
			};
			};
	};		};
	};		};

qcom/sdxlemur.dtsi

+4 −1

Original line number	Original line	Diff line number	Diff line
	@@ -16,7 +16,9 @@
	qcom,msm-id = <458 0x10000>;		qcom,msm-id = <458 0x10000>;
	interrupt-parent = <&intc>;		interrupt-parent = <&intc>;

	aliases { };		aliases {
			pci-domain0 = &pcie0; /* PCIe0 domain */
			};

	chosen { };		chosen { };

	@@ -652,3 +654,4 @@
	#include "sdxlemur-ion.dtsi"		#include "sdxlemur-ion.dtsi"
	#include "sdxlemur-usb.dtsi"		#include "sdxlemur-usb.dtsi"
	#include "sdxlemur-pm.dtsi"		#include "sdxlemur-pm.dtsi"
			#include "sdxlemur-pcie.dtsi"