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Commit c049b206 authored by Rick Wertenbroek's avatar Rick Wertenbroek Committed by Greg Kroah-Hartman
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PCI: rockchip: Add poll and timeout to wait for PHY PLLs to be locked 

commit 9dd3c7c4c8c3f7f010d9cdb7c3f42506d93c9527 upstream.

The RK3399 PCIe controller should wait until the PHY PLLs are locked.
Add poll and timeout to wait for PHY PLLs to be locked. If they cannot
be locked generate error message and jump to error handler. Accessing
registers in the PHY clock domain when PLLs are not locked causes hang
The PHY PLLs status is checked through a side channel register.
This is documented in the TRM section 17.5.8.1 "PCIe Initialization
Sequence".

Link: https://lore.kernel.org/r/20230418074700.1083505-5-rick.wertenbroek@gmail.com


Fixes: cf590b07 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller")
Tested-by: default avatarDamien Le Moal <dlemoal@kernel.org>
Signed-off-by: default avatarRick Wertenbroek <rick.wertenbroek@gmail.com>
Signed-off-by: default avatarLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: default avatarDamien Le Moal <dlemoal@kernel.org>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent a1f311d4

drivers/pci/controller/pcie-rockchip.c

+17 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/gpio/consumer.h>

#include <linux/iopoll.h>

#include <linux/of_pci.h>

#include <linux/phy/phy.h>

#include <linux/platform_device.h>
@@ -154,6 +155,12 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) 
}

EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt);



#define rockchip_pcie_read_addr(addr) rockchip_pcie_read(rockchip, addr)

/* 100 ms max wait time for PHY PLLs to lock */

#define RK_PHY_PLL_LOCK_TIMEOUT_US 100000

/* Sleep should be less than 20ms */

#define RK_PHY_PLL_LOCK_SLEEP_US 1000



int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)

{

	struct device *dev = rockchip->dev;
@@ -255,6 +262,16 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) 
		}

	}



	err = readx_poll_timeout(rockchip_pcie_read_addr,

				 PCIE_CLIENT_SIDE_BAND_STATUS,

				 regs, !(regs & PCIE_CLIENT_PHY_ST),

				 RK_PHY_PLL_LOCK_SLEEP_US,

				 RK_PHY_PLL_LOCK_TIMEOUT_US);

	if (err) {

		dev_err(dev, "PHY PLLs could not lock, %d\n", err);

		goto err_power_off_phy;

	}



	/*

	 * Please don't reorder the deassert sequence of the following

	 * four reset pins.

drivers/pci/controller/pcie-rockchip.h

+2 −0
Original line number Diff line number Diff line
@@ -37,6 +37,8 @@ 
#define   PCIE_CLIENT_MODE_EP            HIWORD_UPDATE(0x0040, 0)

#define   PCIE_CLIENT_GEN_SEL_1		  HIWORD_UPDATE(0x0080, 0)

#define   PCIE_CLIENT_GEN_SEL_2		  HIWORD_UPDATE_BIT(0x0080)

#define PCIE_CLIENT_SIDE_BAND_STATUS	(PCIE_CLIENT_BASE + 0x20)

#define   PCIE_CLIENT_PHY_ST			BIT(12)

#define PCIE_CLIENT_DEBUG_OUT_0		(PCIE_CLIENT_BASE + 0x3c)

#define   PCIE_CLIENT_DEBUG_LTSSM_MASK		GENMASK(5, 0)

#define   PCIE_CLIENT_DEBUG_LTSSM_L1		0x18