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Commit c02762eb authored by Huy Nguyen's avatar Huy Nguyen Committed by Saeed Mahameed
Browse files

net/mlx5: QCAM register firmware command support 



The QCAM register provides capability bit for all the QoS registers
using ACCESS_REG command.

Signed-off-by: default avatarHuy Nguyen <huyn@mellanox.com>
Reviewed-by: default avatarParav Pandit <parav@mellanox.com>
Reviewed-by: default avatarOr Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
parent ee205981

drivers/net/ethernet/mellanox/mlx5/core/fw.c

+10 −0
Original line number Diff line number Diff line
@@ -106,6 +106,13 @@ static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev) 
				   MLX5_MCAM_REGS_FIRST_128);

}



static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)

{

	return mlx5_query_qcam_reg(dev, dev->caps.qcam,

				   MLX5_QCAM_FEATURE_ENHANCED_FEATURES,

				   MLX5_QCAM_REGS_FIRST_128);

}



int mlx5_query_hca_caps(struct mlx5_core_dev *dev)

{

	int err;
@@ -182,6 +189,9 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev) 
	if (MLX5_CAP_GEN(dev, mcam_reg))

		mlx5_get_mcam_reg(dev);



	if (MLX5_CAP_GEN(dev, qcam_reg))

		mlx5_get_qcam_reg(dev);



	return 0;

}

drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h

+2 −0
Original line number Diff line number Diff line
@@ -122,6 +122,8 @@ int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group, 
			u8 access_reg_group);

int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group,

			u8 access_reg_group);

int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,

			u8 feature_group, u8 access_reg_group);



void mlx5_lag_add(struct mlx5_core_dev *dev, struct net_device *netdev);

void mlx5_lag_remove(struct mlx5_core_dev *dev);

drivers/net/ethernet/mellanox/mlx5/core/port.c

+12 −0
Original line number Diff line number Diff line
@@ -98,6 +98,18 @@ int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcam, u8 feature_group, 
	return mlx5_core_access_reg(dev, in, sz, mcam, sz, MLX5_REG_MCAM, 0, 0);

}



int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,

			u8 feature_group, u8 access_reg_group)

{

	u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {};

	int sz = MLX5_ST_SZ_BYTES(qcam_reg);



	MLX5_SET(qcam_reg, in, feature_group, feature_group);

	MLX5_SET(qcam_reg, in, access_reg_group, access_reg_group);



	return mlx5_core_access_reg(mdev, in, sz, qcam, sz, MLX5_REG_QCAM, 0, 0);

}



struct mlx5_reg_pcap {

	u8			rsvd0;

	u8			port_num;

include/linux/mlx5/device.h

+14 −0
Original line number Diff line number Diff line
@@ -1000,6 +1000,14 @@ enum mlx5_mcam_feature_groups { 
	MLX5_MCAM_FEATURE_ENHANCED_FEATURES         = 0x0,

};



enum mlx5_qcam_reg_groups {

	MLX5_QCAM_REGS_FIRST_128                    = 0x0,

};



enum mlx5_qcam_feature_groups {

	MLX5_QCAM_FEATURE_ENHANCED_FEATURES         = 0x0,

};



/* GET Dev Caps macros */

#define MLX5_CAP_GEN(mdev, cap) \

	MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
@@ -1108,6 +1116,12 @@ enum mlx5_mcam_feature_groups { 
#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \

	MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)



#define MLX5_CAP_QCAM_REG(mdev, fld) \

	MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)



#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \

	MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)



#define MLX5_CAP_FPGA(mdev, cap) \

	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)

include/linux/mlx5/driver.h

+2 −0
Original line number Diff line number Diff line
@@ -109,6 +109,7 @@ enum { 
enum {

	MLX5_REG_QETCR		 = 0x4005,

	MLX5_REG_QTCT		 = 0x400a,

	MLX5_REG_QCAM            = 0x4019,

	MLX5_REG_DCBX_PARAM      = 0x4020,

	MLX5_REG_DCBX_APP        = 0x4021,

	MLX5_REG_FPGA_CAP	 = 0x4022,
@@ -798,6 +799,7 @@ struct mlx5_core_dev { 
		u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];

		u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];

		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];

		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];

	} caps;

	phys_addr_t		iseg_base;

	struct mlx5_init_seg __iomem *iseg;