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Commit bfc97f9f authored by Doug Berger's avatar Doug Berger Committed by Will Deacon
Browse files

arm64: apply ARM64_ERRATUM_845719 workaround for Brahma-B53 core 



The Broadcom Brahma-B53 core is susceptible to the issue described by
ARM64_ERRATUM_845719 so this commit enables the workaround to be applied
when executing on that core.

Since there are now multiple entries to match, we must convert the
existing ARM64_ERRATUM_845719 into an erratum list.

Signed-off-by: default avatarDoug Berger <opendmb@gmail.com>
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 36c602dc

Documentation/arm64/silicon-errata.rst

+3 −0
Original line number Diff line number Diff line
@@ -91,6 +91,9 @@ stable kernels. 
| ARM            | MMU-500         | #841119,826419  | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Broadcom       | Brahma-B53      | N/A             | ARM64_ERRATUM_845719        |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Cavium         | ThunderX ITS    | #22375,24313    | CAVIUM_ERRATUM_22375        |

+----------------+-----------------+-----------------+-----------------------------+

| Cavium         | ThunderX ITS    | #23144          | CAVIUM_ERRATUM_23144        |

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@ 
#define CAVIUM_CPU_PART_THUNDERX_83XX	0x0A3

#define CAVIUM_CPU_PART_THUNDERX2	0x0AF



#define BRCM_CPU_PART_BRAHMA_B53	0x100

#define BRCM_CPU_PART_VULCAN		0x516



#define QCOM_CPU_PART_FALKOR_V1		0x800
@@ -105,6 +106,7 @@ 
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)

#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)

#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)

#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)

#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)

arch/arm64/kernel/cpu_errata.c

+11 −2
Original line number Diff line number Diff line
@@ -743,6 +743,16 @@ static const struct midr_range erratum_1418040_list[] = { 
};

#endif



#ifdef CONFIG_ARM64_ERRATUM_845719

static const struct midr_range erratum_845719_list[] = {

	/* Cortex-A53 r0p[01234] */

	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),

	/* Brahma-B53 r0p[0] */

	MIDR_REV(MIDR_BRAHMA_B53, 0, 0),

	{},

};

#endif



const struct arm64_cpu_capabilities arm64_errata[] = {

#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE

	{
@@ -783,10 +793,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
#endif

#ifdef CONFIG_ARM64_ERRATUM_845719

	{

	/* Cortex-A53 r0p[01234] */

		.desc = "ARM erratum 845719",

		.capability = ARM64_WORKAROUND_845719,

		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),

		ERRATA_MIDR_RANGE_LIST(erratum_845719_list),

	},

#endif

#ifdef CONFIG_CAVIUM_ERRATUM_23154