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Commit bfa709bc authored by Zhuoyu Zhang's avatar Zhuoyu Zhang Committed by Rafael J. Wysocki
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cpufreq: powerpc: add cpufreq transition latency for FSL e500mc SoCs 



According to the data provided by HW Team, at least 12 internal platform
clock cycles are required to stabilize a DFS clock switch on FSL e500mc Socs.
This patch replaces the CPUFREQ_ETERNAL with appropriate HW clock transition
latency to make DFS governors work normally on Freescale e500mc boards.

Signed-off-by: default avatarZhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent 0b443ead

drivers/cpufreq/ppc-corenet-cpufreq.c

+3 −1
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#include <linux/of.h>

#include <linux/slab.h>

#include <linux/smp.h>

#include <sysdev/fsl_soc.h>



/**

 * struct cpu_data - per CPU data struct
@@ -205,7 +206,8 @@ static int corenet_cpufreq_cpu_init(struct cpufreq_policy *policy) 
	for_each_cpu(i, per_cpu(cpu_mask, cpu))

		per_cpu(cpu_data, i) = data;



	policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;

	policy->cpuinfo.transition_latency =

				(12 * NSEC_PER_SEC) / fsl_get_sys_freq();

	of_node_put(np);



	return 0;