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Commit bf5a01d7 authored by Leonard Crestez's avatar Leonard Crestez Committed by Shawn Guo
Browse files

ARM: imx6ull: Make suspend/resume work like on 6ul 



Suspend and resume on imx6ull is currenty not working because of some
missed checks where behavior should match imx6ul.

Signed-off-by: default avatarLeonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent b3ea5757

arch/arm/mach-imx/pm-imx6.c

+4 −2
Original line number Diff line number Diff line
@@ -295,7 +295,8 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) 
		val &= ~BM_CLPCR_SBYOS;

		if (cpu_is_imx6sl())

			val |= BM_CLPCR_BYPASS_PMIC_READY;

		if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul())

		if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||

		    cpu_is_imx6ull())

			val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;

		else

			val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
@@ -312,7 +313,8 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) 
		val |= BM_CLPCR_SBYOS;

		if (cpu_is_imx6sl() || cpu_is_imx6sx())

			val |= BM_CLPCR_BYPASS_PMIC_READY;

		if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul())

		if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||

		    cpu_is_imx6ull())

			val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;

		else

			val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;