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Commit bf50bcc2 authored by Sascha Hauer's avatar Sascha Hauer
Browse files

mx2: Codingstyle: Let the compiler count arrays 



Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
parent aa68c027

arch/arm/mach-mx2/devices.c

+73 −92
Original line number Diff line number Diff line
@@ -41,20 +41,18 @@ 


/*

 * General Purpose Timer

 * - i.MX1: 2 timer (slighly different register handling)

 * - i.MX21: 3 timer

 * - i.MX27: 6 timer

 * - i.MX21: 3 timers

 * - i.MX27: 6 timers

 */



/* We use gpt0 as system timer, so do not add a device for this one */



static struct resource timer1_resources[] = {

	[0] = {

	{

		.start	= GPT2_BASE_ADDR,

		.end	= GPT2_BASE_ADDR + 0x17,

		.flags	= IORESOURCE_MEM

	},

	[1] = {

		.flags	= IORESOURCE_MEM,

	}, {

		.start   = MXC_INT_GPT2,

		.end     = MXC_INT_GPT2,

		.flags   = IORESOURCE_IRQ,
@@ -65,16 +63,15 @@ struct platform_device mxc_gpt1 = { 
	.name = "imx_gpt",

	.id = 1,

	.num_resources = ARRAY_SIZE(timer1_resources),

	.resource = timer1_resources

	.resource = timer1_resources,

};



static struct resource timer2_resources[] = {

	[0] = {

	{

		.start	= GPT3_BASE_ADDR,

		.end	= GPT3_BASE_ADDR + 0x17,

		.flags	= IORESOURCE_MEM

	},

	[1] = {

		.flags	= IORESOURCE_MEM,

	}, {

		.start   = MXC_INT_GPT3,

		.end     = MXC_INT_GPT3,

		.flags   = IORESOURCE_IRQ,
@@ -85,17 +82,16 @@ struct platform_device mxc_gpt2 = { 
	.name = "imx_gpt",

	.id = 2,

	.num_resources = ARRAY_SIZE(timer2_resources),

	.resource = timer2_resources

	.resource = timer2_resources,

};



#ifdef CONFIG_MACH_MX27

static struct resource timer3_resources[] = {

	[0] = {

	{

		.start	= GPT4_BASE_ADDR,

		.end	= GPT4_BASE_ADDR + 0x17,

		.flags	= IORESOURCE_MEM

	},

	[1] = {

		.flags	= IORESOURCE_MEM,

	}, {

		.start   = MXC_INT_GPT4,

		.end     = MXC_INT_GPT4,

		.flags   = IORESOURCE_IRQ,
@@ -106,16 +102,15 @@ struct platform_device mxc_gpt3 = { 
	.name = "imx_gpt",

	.id = 3,

	.num_resources = ARRAY_SIZE(timer3_resources),

	.resource = timer3_resources

	.resource = timer3_resources,

};



static struct resource timer4_resources[] = {

	[0] = {

	{

		.start	= GPT5_BASE_ADDR,

		.end	= GPT5_BASE_ADDR + 0x17,

		.flags	= IORESOURCE_MEM

	},

	[1] = {

		.flags	= IORESOURCE_MEM,

	}, {

		.start   = MXC_INT_GPT5,

		.end     = MXC_INT_GPT5,

		.flags   = IORESOURCE_IRQ,
@@ -126,16 +121,15 @@ struct platform_device mxc_gpt4 = { 
	.name = "imx_gpt",

	.id = 4,

	.num_resources = ARRAY_SIZE(timer4_resources),

	.resource = timer4_resources

	.resource = timer4_resources,

};



static struct resource timer5_resources[] = {

	[0] = {

	{

		.start	= GPT6_BASE_ADDR,

		.end	= GPT6_BASE_ADDR + 0x17,

		.flags	= IORESOURCE_MEM

	},

	[1] = {

		.flags	= IORESOURCE_MEM,

	}, {

		.start   = MXC_INT_GPT6,

		.end     = MXC_INT_GPT6,

		.flags   = IORESOURCE_IRQ,
@@ -146,7 +140,7 @@ struct platform_device mxc_gpt5 = { 
	.name = "imx_gpt",

	.id = 5,

	.num_resources = ARRAY_SIZE(timer5_resources),

	.resource = timer5_resources

	.resource = timer5_resources,

};

#endif
@@ -190,11 +184,11 @@ static struct resource mxc_nand_resources[] = { 
	{

		.start	= NFC_BASE_ADDR,

		.end	= NFC_BASE_ADDR + 0xfff,

		.flags	= IORESOURCE_MEM

		.flags	= IORESOURCE_MEM,

	}, {

		.start	= MXC_INT_NANDFC,

		.end	= MXC_INT_NANDFC,

		.flags	= IORESOURCE_IRQ

		.flags	= IORESOURCE_IRQ,

	},

};
@@ -216,8 +210,7 @@ static struct resource mxc_fb[] = { 
		.start = LCDC_BASE_ADDR,

		.end   = LCDC_BASE_ADDR + 0xFFF,

		.flags = IORESOURCE_MEM,

	},

	{

	}, {

		.start = MXC_INT_LCDC,

		.end   = MXC_INT_LCDC,

		.flags = IORESOURCE_IRQ,
@@ -240,11 +233,11 @@ static struct resource mxc_fec_resources[] = { 
	{

		.start	= FEC_BASE_ADDR,

		.end	= FEC_BASE_ADDR + 0xfff,

		.flags	= IORESOURCE_MEM

		.flags	= IORESOURCE_MEM,

	}, {

		.start	= MXC_INT_FEC,

		.end	= MXC_INT_FEC,

		.flags	= IORESOURCE_IRQ

		.flags	= IORESOURCE_IRQ,

	},

};
@@ -257,15 +250,14 @@ struct platform_device mxc_fec_device = { 
#endif



static struct resource mxc_i2c_1_resources[] = {

	[0] = {

	{

		.start	= I2C_BASE_ADDR,

		.end	= I2C_BASE_ADDR + 0x0fff,

		.flags	= IORESOURCE_MEM

	},

	[1] = {

		.flags	= IORESOURCE_MEM,

	}, {

		.start	= MXC_INT_I2C,

		.end	= MXC_INT_I2C,

		.flags	= IORESOURCE_IRQ

		.flags	= IORESOURCE_IRQ,

	}

};
@@ -273,20 +265,19 @@ struct platform_device mxc_i2c_device0 = { 
	.name = "imx-i2c",

	.id = 0,

	.num_resources = ARRAY_SIZE(mxc_i2c_1_resources),

	.resource = mxc_i2c_1_resources

	.resource = mxc_i2c_1_resources,

};



#ifdef CONFIG_MACH_MX27

static struct resource mxc_i2c_2_resources[] = {

	[0] = {

	{

		.start	= I2C2_BASE_ADDR,

		.end	= I2C2_BASE_ADDR + 0x0fff,

		.flags	= IORESOURCE_MEM

	},

	[1] = {

		.flags	= IORESOURCE_MEM,

	}, {

		.start	= MXC_INT_I2C2,

		.end	= MXC_INT_I2C2,

		.flags	= IORESOURCE_IRQ

		.flags	= IORESOURCE_IRQ,

	}

};
@@ -294,17 +285,16 @@ struct platform_device mxc_i2c_device1 = { 
	.name = "imx-i2c",

	.id = 1,

	.num_resources = ARRAY_SIZE(mxc_i2c_2_resources),

	.resource = mxc_i2c_2_resources

	.resource = mxc_i2c_2_resources,

};

#endif



static struct resource mxc_pwm_resources[] = {

	[0] = {

	{

		.start	= PWM_BASE_ADDR,

		.end	= PWM_BASE_ADDR + 0x0fff,

		.flags	= IORESOURCE_MEM

	},

	[1] = {

		.flags	= IORESOURCE_MEM,

	}, {

		.start   = MXC_INT_PWM,

		.end     = MXC_INT_PWM,

		.flags   = IORESOURCE_IRQ,
@@ -315,27 +305,25 @@ struct platform_device mxc_pwm_device = { 
	.name = "mxc_pwm",

	.id = 0,

	.num_resources = ARRAY_SIZE(mxc_pwm_resources),

	.resource = mxc_pwm_resources

	.resource = mxc_pwm_resources,

};



/*

 * Resource definition for the MXC SDHC

 */

static struct resource mxc_sdhc1_resources[] = {

	[0] = {

	{

		.start = SDHC1_BASE_ADDR,

		.end   = SDHC1_BASE_ADDR + SZ_4K - 1,

		.flags = IORESOURCE_MEM,

			},

	[1] = {

	}, {

		.start = MXC_INT_SDHC1,

		.end   = MXC_INT_SDHC1,

		.flags = IORESOURCE_IRQ,

			},

	[2] = {

	}, {

		.start  = DMA_REQ_SDHC1,

		.end    = DMA_REQ_SDHC1,

			.flags  = IORESOURCE_DMA

		.flags  = IORESOURCE_DMA,

	},

};
@@ -353,20 +341,18 @@ struct platform_device mxc_sdhc_device0 = { 
};



static struct resource mxc_sdhc2_resources[] = {

	[0] = {

	{

		.start = SDHC2_BASE_ADDR,

		.end   = SDHC2_BASE_ADDR + SZ_4K - 1,

		.flags = IORESOURCE_MEM,

			},

	[1] = {

	}, {

		.start = MXC_INT_SDHC2,

		.end   = MXC_INT_SDHC2,

		.flags = IORESOURCE_IRQ,

			},

	[2] = {

	}, {

		.start  = DMA_REQ_SDHC2,

		.end    = DMA_REQ_SDHC2,

			.flags  = IORESOURCE_DMA

		.flags  = IORESOURCE_DMA,

	},

};
@@ -385,33 +371,28 @@ struct platform_device mxc_sdhc_device1 = { 


/* GPIO port description */

static struct mxc_gpio_port imx_gpio_ports[] = {

	[0] = {

	{

		.chip.label = "gpio-0",

		.irq = MXC_INT_GPIO,

		.base = IO_ADDRESS(GPIO_BASE_ADDR),

		.virtual_irq_start = MXC_GPIO_IRQ_START,

	},

	[1] = {

	}, {

		.chip.label = "gpio-1",

		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),

		.virtual_irq_start = MXC_GPIO_IRQ_START + 32,

	},

	[2] = {

	}, {

		.chip.label = "gpio-2",

		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),

		.virtual_irq_start = MXC_GPIO_IRQ_START + 64,

	},

	[3] = {

	}, {

		.chip.label = "gpio-3",

		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),

		.virtual_irq_start = MXC_GPIO_IRQ_START + 96,

	},

	[4] = {

	}, {

		.chip.label = "gpio-4",

		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),

		.virtual_irq_start = MXC_GPIO_IRQ_START + 128,

	},

	[5] = {

	}, {

		.chip.label = "gpio-5",

		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),

		.virtual_irq_start = MXC_GPIO_IRQ_START + 160,