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Commit bf3c425e authored by Madhuri Medasani's avatar Madhuri Medasani
Browse files

ARM: dts: msm: Add support for GCC for BLAIR 

Enable Global clock controller for BLAIR. While
at it, disable other clock nodes and Use dummy rpm
clock driver for BLAIR RUMI.

Change-Id: I43ac592528cb5f23d21073a4d1835da387a0814f
parent f549366d

qcom/blair-rumi.dtsi

+25 −0
Original line number Diff line number Diff line
@@ -26,6 +26,22 @@ 
				     0x10060 0x3c

				     0x0 0x4>;

	};



	bi_tcxo: bi_tcxo {

		compatible = "fixed-factor-clock";

		clock-mult = <1>;

		clock-div = <2>;

		clocks = <&xo_board>;

		#clock-cells = <0>;

	 };



	bi_tcxo_ao: bi_tcxo_ao {

		compatible = "fixed-factor-clock";

		clock-mult = <1>;

		clock-div = <2>;

		clocks = <&xo_board>;

		#clock-cells = <0>;

	};

};



&tsens0 {
@@ -124,3 +140,12 @@ 
&rpm_bus {

	rpm-standalone;

};



&rpmcc {

	compatible = "qcom,dummycc";

	clock-output-names = "rpmhcc_clocks";

};



&gcc {

	clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>;

};

qcom/blair.dtsi

+9 −4
Original line number Diff line number Diff line 
#include <dt-bindings/clock/qcom,dispcc-holi.h>

#include <dt-bindings/clock/qcom,gcc-holi.h>

#include <dt-bindings/clock/qcom,gpucc-holi.h>

#include <dt-bindings/clock/qcom,dispcc-blair.h>

#include <dt-bindings/clock/qcom,gcc-blair.h>

#include <dt-bindings/clock/qcom,gpucc-blair.h>

#include <dt-bindings/clock/qcom,rpmcc.h>

#include <dt-bindings/interconnect/qcom,cpucp-l3.h>

#include <dt-bindings/interconnect/qcom,holi.h>
@@ -1176,7 +1176,7 @@ 
	};



	gcc: clock-controller@1400000 {

		compatible = "qcom,holi-gcc", "syscon";

		compatible = "qcom,blair-gcc", "syscon";

		reg = <0x1400000 0x1f0000>;

		reg_names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;
@@ -1199,6 +1199,7 @@ 
		clock-names = "bi_tcxo", "gcc_disp_gpll0_clk";

		#clock-cells = <1>;

		#reset-cells = <1>;

		status = "disabled";

	};



	gpucc: clock-controller@5990000 {
@@ -1216,6 +1217,7 @@ 
				"gcc_gpu_snoc_dvm_gfx_clk";

		#clock-cells = <1>;

		#reset-cells = <1>;

		status = "disabled";

	};



	cpucc: syscon@faa0018 {
@@ -1238,6 +1240,7 @@ 
		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;

		clock-names = "xo_clk_src";

		#clock-cells = <1>;

		status = "disabled";

	};



	cpufreq_hw: qcom,cpufreq-hw {
@@ -1256,6 +1259,7 @@ 
				<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "dcvsh0_int", "dcvsh1_int";

		#freq-domain-cells = <2>;

		status = "disabled";

	};



	qcom,cpufreq-hw-debug@0fd91000 {
@@ -1263,6 +1267,7 @@ 
		reg = <0x0fd91000 0x800>;

		reg-names = "domain-top";

		qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>;

		status = "disabled";

	};



	ddr_bw_opp_table: ddr-bw-opp-table {