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Commit becfc5e9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-next-2018-06-15' of git://anongit.freedesktop.org/drm/drm 

Pull amd drm fixes from Dave Airlie:
 "Just a single set of AMD fixes for stuff in -next for -rc1"

* tag 'drm-next-2018-06-15' of git://anongit.freedesktop.org/drm/drm: (47 commits)
  drm/amd/powerplay: Set higher SCLK&MCLK frequency than dpm7 in OD (v2)
  drm/amd/powerplay: remove uncessary extra gfxoff control call
  drm/amdgpu: fix parsing indirect register list v2
  drm/amd/include: Update df 3.6 mask and shift definition
  drm/amd/pp: Fix OD feature enable failed on Vega10 workstation cards
  drm/amd/display: Fix stale buffer object (bo) use
  drm/amd/pp: initialize result to before or'ing in data
  drm/amd/powerplay: fix wrong clock adjust sequence
  drm/amdgpu: Grab/put runtime PM references in atomic_commit_tail()
  drm/amd/powerplay: fix missed hwmgr check warning before call gfx_off_control handler
  drm/amdgpu: fix CG enabling hang with gfxoff enabled
  drm/amdgpu: fix clear_all and replace handling in the VM (v2)
  drm/amdgpu: add checking for sos version
  drm/amdgpu: fix the missed vcn fw version report
  Revert "drm/amdgpu: Add an ATPX quirk for hybrid laptop"
  drm/amdgpu/df: fix potential array out-of-bounds read
  drm/amdgpu: Fix NULL pointer when load kfd driver with PP block is disabled
  drm/gfx9: Update gc goldensetting for vega20.
  drm/amd/pp: Allow underclocking when od table is empty in vbios
  drm/amdgpu/display: check if ppfuncs exists before using it
  ...
parents b5d903c2 daf0678c

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+7 −11
Original line number Original line Diff line number Diff line
@@ -342,15 +342,12 @@ void get_local_mem_info(struct kgd_dev *kgd, 
			mem_info->local_mem_size_public,

			mem_info->local_mem_size_public,

			mem_info->local_mem_size_private);

			mem_info->local_mem_size_private);





	if (amdgpu_emu_mode == 1) {

		mem_info->mem_clk_max = 100;

		return;

	}



	if (amdgpu_sriov_vf(adev))

	if (amdgpu_sriov_vf(adev))

		mem_info->mem_clk_max = adev->clock.default_mclk / 100;

		mem_info->mem_clk_max = adev->clock.default_mclk / 100;

	else

	else if (adev->powerplay.pp_funcs)

		mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;

		mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;

	else

		mem_info->mem_clk_max = 100;

}

}





uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)

uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
@@ -367,13 +364,12 @@ uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd) 
	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;





	/* the sclk is in quantas of 10kHz */

	/* the sclk is in quantas of 10kHz */

	if (amdgpu_emu_mode == 1)

		return 100;



	if (amdgpu_sriov_vf(adev))

	if (amdgpu_sriov_vf(adev))

		return adev->clock.default_sclk / 100;

		return adev->clock.default_sclk / 100;



	else if (adev->powerplay.pp_funcs)

		return amdgpu_dpm_get_sclk(adev, false) / 100;

		return amdgpu_dpm_get_sclk(adev, false) / 100;

	else

		return 100;

}

}





void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)

void get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)

drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c

+0 −1
Original line number Original line Diff line number Diff line
@@ -569,7 +569,6 @@ static const struct amdgpu_px_quirk amdgpu_px_quirk_list[] = { 
	{ 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },

	{ 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },

	{ 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },

	{ 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },

	{ 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },

	{ 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },

	{ 0x1002, 0x67DF, 0x1028, 0x0774, AMDGPU_PX_QUIRK_FORCE_ATPX },

	{ 0, 0, 0, 0, 0 },

	{ 0, 0, 0, 0, 0 },

};

};

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+23 −15
Original line number Original line Diff line number Diff line
@@ -522,6 +522,9 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, 
	struct amdgpu_bo_list_entry *e;

	struct amdgpu_bo_list_entry *e;

	struct list_head duplicates;

	struct list_head duplicates;

	unsigned i, tries = 10;

	unsigned i, tries = 10;

	struct amdgpu_bo *gds;

	struct amdgpu_bo *gws;

	struct amdgpu_bo *oa;

	int r;

	int r;





	INIT_LIST_HEAD(&p->validated);

	INIT_LIST_HEAD(&p->validated);
@@ -652,18 +655,24 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, 




	amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,

	amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,

				     p->bytes_moved_vis);

				     p->bytes_moved_vis);



	if (p->bo_list) {

	if (p->bo_list) {

		struct amdgpu_bo *gds = p->bo_list->gds_obj;

		struct amdgpu_bo *gws = p->bo_list->gws_obj;

		struct amdgpu_bo *oa = p->bo_list->oa_obj;

		struct amdgpu_vm *vm = &fpriv->vm;

		struct amdgpu_vm *vm = &fpriv->vm;

		unsigned i;

		unsigned i;





		gds = p->bo_list->gds_obj;

		gws = p->bo_list->gws_obj;

		oa = p->bo_list->oa_obj;

		for (i = 0; i < p->bo_list->num_entries; i++) {

		for (i = 0; i < p->bo_list->num_entries; i++) {

			struct amdgpu_bo *bo = p->bo_list->array[i].robj;

			struct amdgpu_bo *bo = p->bo_list->array[i].robj;





			p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);

			p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);

		}

		}

	} else {

		gds = p->adev->gds.gds_gfx_bo;

		gws = p->adev->gds.gws_gfx_bo;

		oa = p->adev->gds.oa_gfx_bo;

	}





	if (gds) {

	if (gds) {

		p->job->gds_base = amdgpu_bo_gpu_offset(gds);

		p->job->gds_base = amdgpu_bo_gpu_offset(gds);
@@ -677,7 +686,6 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, 
		p->job->oa_base = amdgpu_bo_gpu_offset(oa);

		p->job->oa_base = amdgpu_bo_gpu_offset(oa);

		p->job->oa_size = amdgpu_bo_size(oa);

		p->job->oa_size = amdgpu_bo_size(oa);

	}

	}

	}





	if (!r && p->uf_entry.robj) {

	if (!r && p->uf_entry.robj) {

		struct amdgpu_bo *uf = p->uf_entry.robj;

		struct amdgpu_bo *uf = p->uf_entry.robj;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+12 −0
Original line number Original line Diff line number Diff line
@@ -1730,6 +1730,18 @@ static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev) 
			}

			}

		}

		}

	}

	}



	if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) {

		/* enable gfx powergating */

		amdgpu_device_ip_set_powergating_state(adev,

						       AMD_IP_BLOCK_TYPE_GFX,

						       AMD_PG_STATE_GATE);

		/* enable gfxoff */

		amdgpu_device_ip_set_powergating_state(adev,

						       AMD_IP_BLOCK_TYPE_SMC,

						       AMD_PG_STATE_GATE);

	}



	return 0;

	return 0;

}

}

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

+12 −3
Original line number Original line Diff line number Diff line
@@ -30,6 +30,7 @@ 
#include <drm/drmP.h>

#include <drm/drmP.h>

#include <drm/amdgpu_drm.h>

#include <drm/amdgpu_drm.h>

#include "amdgpu.h"

#include "amdgpu.h"

#include "amdgpu_display.h"





void amdgpu_gem_object_free(struct drm_gem_object *gobj)

void amdgpu_gem_object_free(struct drm_gem_object *gobj)

{

{
@@ -235,6 +236,13 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 
	/* create a gem object to contain this object in */

	/* create a gem object to contain this object in */

	if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |

	if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |

	    AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {

	    AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {

		if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {

			/* if gds bo is created from user space, it must be

			 * passed to bo list

			 */

			DRM_ERROR("GDS bo cannot be per-vm-bo\n");

			return -EINVAL;

		}

		flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;

		flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;

		if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)

		if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)

			size = size << AMDGPU_GDS_SHIFT;

			size = size << AMDGPU_GDS_SHIFT;
@@ -749,15 +757,16 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv, 
	struct amdgpu_device *adev = dev->dev_private;

	struct amdgpu_device *adev = dev->dev_private;

	struct drm_gem_object *gobj;

	struct drm_gem_object *gobj;

	uint32_t handle;

	uint32_t handle;

	u32 domain;

	int r;

	int r;





	args->pitch = amdgpu_align_pitch(adev, args->width,

	args->pitch = amdgpu_align_pitch(adev, args->width,

					 DIV_ROUND_UP(args->bpp, 8), 0);

					 DIV_ROUND_UP(args->bpp, 8), 0);

	args->size = (u64)args->pitch * args->height;

	args->size = (u64)args->pitch * args->height;

	args->size = ALIGN(args->size, PAGE_SIZE);

	args->size = ALIGN(args->size, PAGE_SIZE);



	domain = amdgpu_bo_get_preferred_pin_domain(adev,

	r = amdgpu_gem_object_create(adev, args->size, 0,

				amdgpu_display_supported_domains(adev));

				     AMDGPU_GEM_DOMAIN_VRAM,

	r = amdgpu_gem_object_create(adev, args->size, 0, domain,

				     AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,

				     AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,

				     false, NULL, &gobj);

				     false, NULL, &gobj);

	if (r)

	if (r)