Loading drivers/cam_icp/cam_icp_subdev.c +1 −1 Original line number Diff line number Diff line Loading @@ -205,7 +205,7 @@ static int cam_icp_component_bind(struct device *dev, g_icp_dev.open_cnt = 0; mutex_init(&g_icp_dev.icp_lock); CAM_INFO(CAM_ICP, "Component bound successfully"); CAM_DBG(CAM_ICP, "Component bound successfully"); return rc; Loading drivers/cam_isp/cam_isp_dev.c +1 −1 Original line number Diff line number Diff line Loading @@ -161,7 +161,7 @@ static int cam_isp_dev_component_bind(struct device *dev, mutex_init(&g_isp_dev.isp_mutex); CAM_INFO(CAM_ISP, "Component bound successfully"); CAM_DBG(CAM_ISP, "Component bound successfully"); return 0; unregister: Loading drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.c +1 −1 Original line number Diff line number Diff line Loading @@ -149,7 +149,7 @@ int cam_vfe_init_soc_resources(struct cam_hw_soc_info *soc_info, CAM_VFE_DSP_CLK_NAME, &soc_private->dsp_clk, &soc_private->dsp_clk_index, &soc_private->dsp_clk_rate); if (rc) CAM_WARN(CAM_ISP, "Option clk get failed with rc %d", rc); CAM_DBG(CAM_ISP, "Option clk get failed with rc %d", rc); rc = cam_vfe_request_platform_resource(soc_info, vfe_irq_handler, irq_data); Loading drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c +1 −1 Original line number Diff line number Diff line Loading @@ -3559,7 +3559,7 @@ static int cam_vfe_bus_ver3_init_hw(void *hw_priv, } /* no clock gating at bus input */ CAM_INFO(CAM_ISP, "Overriding clock gating at bus input"); CAM_DBG(CAM_ISP, "Overriding clock gating at bus input"); cam_io_w_mb(0x3FFFFFF, bus_priv->common_data.mem_base + bus_priv->common_data.common_reg->cgc_ovd); Loading drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c +1 −1 Original line number Diff line number Diff line Loading @@ -340,7 +340,7 @@ int cam_vfe_top_ver3_init_hw(void *device_priv, * Auto clock gating is enabled by default, but no harm * in setting the value we expect. */ CAM_INFO(CAM_ISP, "Enabling clock gating at IFE top"); CAM_DBG(CAM_ISP, "Enabling clock gating at IFE top"); cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, common_data.common_reg->core_cgc_ovd_0, 0x0); Loading Loading
drivers/cam_icp/cam_icp_subdev.c +1 −1 Original line number Diff line number Diff line Loading @@ -205,7 +205,7 @@ static int cam_icp_component_bind(struct device *dev, g_icp_dev.open_cnt = 0; mutex_init(&g_icp_dev.icp_lock); CAM_INFO(CAM_ICP, "Component bound successfully"); CAM_DBG(CAM_ICP, "Component bound successfully"); return rc; Loading
drivers/cam_isp/cam_isp_dev.c +1 −1 Original line number Diff line number Diff line Loading @@ -161,7 +161,7 @@ static int cam_isp_dev_component_bind(struct device *dev, mutex_init(&g_isp_dev.isp_mutex); CAM_INFO(CAM_ISP, "Component bound successfully"); CAM_DBG(CAM_ISP, "Component bound successfully"); return 0; unregister: Loading
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.c +1 −1 Original line number Diff line number Diff line Loading @@ -149,7 +149,7 @@ int cam_vfe_init_soc_resources(struct cam_hw_soc_info *soc_info, CAM_VFE_DSP_CLK_NAME, &soc_private->dsp_clk, &soc_private->dsp_clk_index, &soc_private->dsp_clk_rate); if (rc) CAM_WARN(CAM_ISP, "Option clk get failed with rc %d", rc); CAM_DBG(CAM_ISP, "Option clk get failed with rc %d", rc); rc = cam_vfe_request_platform_resource(soc_info, vfe_irq_handler, irq_data); Loading
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c +1 −1 Original line number Diff line number Diff line Loading @@ -3559,7 +3559,7 @@ static int cam_vfe_bus_ver3_init_hw(void *hw_priv, } /* no clock gating at bus input */ CAM_INFO(CAM_ISP, "Overriding clock gating at bus input"); CAM_DBG(CAM_ISP, "Overriding clock gating at bus input"); cam_io_w_mb(0x3FFFFFF, bus_priv->common_data.mem_base + bus_priv->common_data.common_reg->cgc_ovd); Loading
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c +1 −1 Original line number Diff line number Diff line Loading @@ -340,7 +340,7 @@ int cam_vfe_top_ver3_init_hw(void *device_priv, * Auto clock gating is enabled by default, but no harm * in setting the value we expect. */ CAM_INFO(CAM_ISP, "Enabling clock gating at IFE top"); CAM_DBG(CAM_ISP, "Enabling clock gating at IFE top"); cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, common_data.common_reg->core_cgc_ovd_0, 0x0); Loading